VHDL and VIEWLOGIC 
Author Message
 VHDL and VIEWLOGIC

We have just received the "Workview plus" EDA package.
We are specially interested in the methodology to be
used from the VHDL specification to the hardware
realization. We feel a little bit lost with the
"Viewlogic" documentation.

Do you know references of any book or document that can
help us?
Is there anything like a Viewlogic users group ?
Is there a tutorial that spans the complete design process
from VHDL specification to the HW realization (for example
FPGA) ?



Tue, 08 Apr 1997 18:43:40 GMT  
 VHDL and VIEWLOGIC
: We have just received the "Workview plus" EDA package.
: We are specially interested in the methodology to be
: used from the VHDL specification to the hardware
: realization. We feel a little bit lost with the
: "Viewlogic" documentation.

: Do you know references of any book or document that can
: help us?
: Is there anything like a Viewlogic users group ?
: Is there a tutorial that spans the complete design process
: from VHDL specification to the HW realization (for example
: FPGA) ?

1) Review teh FAQ
2) Get the VHDL-Cookbook.  Available at ftp.cs.adelaide.edu.au pub/VHDL/

This will help free!

The FAQ lists sources for books, etc.



Tue, 08 Apr 1997 23:18:57 GMT  
 VHDL and VIEWLOGIC
We've used the ViewLogic environment for quite a few years, and we
despise it thoroughly.  Their synthesizer is horrible (although its
probably acceptable if you are only going up to 10MHz or so) and their
own VHDL is incredibly limited (...WHAT...? I can't use a GENERATE
statement...!!!!  If I assign different bits of a bus from different
processes the entire bus goes 'X'...?  What's with this 'VLBIT' stuff?
You don't support std_logic....?  Yuck)

They have lots of glitzy literature, lots of GUI on-line documentation
etc., (where the useful features are un-documented) but no substance
for an ASIC engineer.  It looks like they tried to retrofit an ASIC
digital package onto a schematic capture/PCB package.  The result is a
huge mess.

Unfortunately, ViewLogic is buying all sorts of companies and
re-marketing their products as their own (for example, the Vantage
VHDL compiler is now badly integrated into the ViewLogic VHDL).
Hopefully the bad ViewLogic quality won't destroy products that
they now own that are actually useful (Motive, Vantage, etc.)

We're getting away from it as fast as we can convert our files over to
something else.  We've switched to Vantage (20 times faster, although
unfortunately ViewLogic now owns them) for our simulation and Synopsys
for synthesis.

Please reconsider your decision to use ViewLogic, you'll hate yourself
for getting stuck with them once you see what the alternatives are.
--
     Michael Smith - SMP Chipset Design Engineer


Fax:   (416) 620-5005

    _/     _/_/   _/_/_/   _/                   _/
   _/    _/        _/     _/
  _/      _/_/    _/     _/     _/_/_/ _/_/_/ _/ _/_/_/
 _/         _/   _/     _/     _/  _/ _/  _/ _/ _/
_/_/_/ _/_/_/ _/_/_/   _/_/_/ _/_/_/ _/_/_/ _/ _/_/_/
                                        _/   LSI Logic Corp. of Canada, Inc.
                                   _/_/_/   Suite 1110, 401 The West Mall
                                           Etobicoke, Ontario
                                          M9C 5J5



Fri, 11 Apr 1997 23:03:13 GMT  
 VHDL and VIEWLOGIC

=>Viewlogic VHDL is a waste of money and time. If you lost now wait till
=>you get more involved with it!
=>
=>Bye
=>
=>Nael
=>

Could you explain this a bit more? Why is it a waste of money/time, what
are the advantages of other systems, etc.

Andries
---
------------------------------------
| Message is author's opinion only |
|                                  |
| Andries Kruithof                 |
| Schlumberger Geco-Prakla         |

------------------------------------



Fri, 11 Apr 1997 21:53:53 GMT  
 VHDL and VIEWLOGIC
Viewlogic VHDL is a waste of money and time. If you lost now wait till
you get more involved with it!

Bye

Nael

Quote:

> We have just received the "Workview plus" EDA package.
> We are specially interested in the methodology to be
> used from the VHDL specification to the hardware
> realization. We feel a little bit lost with the
> "Viewlogic" documentation.

> Do you know references of any book or document that can
> help us?
> Is there anything like a Viewlogic users group ?
> Is there a tutorial that spans the complete design process
> from VHDL specification to the HW realization (for example
> FPGA) ?



Wed, 09 Apr 1997 00:39:44 GMT  
 VHDL and VIEWLOGIC

Quote:

> (Michael Smith) writes:

> We've used the ViewLogic environment for quite a few years, and we
> despise it thoroughly.  Their synthesizer is horrible (although its
> probably acceptable if you are only going up to 10MHz or so) and their
> own VHDL is incredibly limited (...WHAT...? I can't use a GENERATE
> statement...!!!!  If I assign different bits of a bus from different
> processes the entire bus goes 'X'...?  What's with this 'VLBIT' stuff?
> You don't support std_logic....?  Yuck)

> (deleted stuff)

> Please reconsider your decision to use ViewLogic, you'll hate yourself
> for getting stuck with them once you see what the alternatives are.

> ---BS. Do use your head in making a decision & consider the alternatives.
> I'm quite sorry that this fellow has a problem with our tools, but no one
> claims absolute perfection in CAE, and if they do they are less that
> honest...
> Besides, could the 20-30% growth rate we're seeing be the result of smoke
> and mirrors ? No...I'd say it's from companies who DID consider the
> alternatives...

>                                  -A.D. Stone - AE-SF Peninsula, Viewlogic

Just thought I'd throw out my $.02 worth:

     I have never used Viewlogic, but since 1986 I have used LSI's proprietary
design environment (LSED, LSIM, etc...), Mentor, a Unisys inhouse design tool,
Synopsys, IKOS, and Cadence (Concept, Leapfrog).  Some tools have been clearly
better than others, but they have all have their share of pains and problems.
     I agree with Mr. Stone of Viewlogic that perfection cannot be attained in
CAE (or anywhere else for that matter).  I also understand how Mr. Smith feels
because I've been there, too.  My group has had *serious* problems w/ Leapfrog
randomly crashing and I think Concept is painful (at best) to use, yet I know
the other options have their own set of problems.  
     The best thing we can do as users is to make as educated of a decision as
possible when chosing a CAE design tool, and then work with the vendor to fix
its problems and make it better.  Sure, there is a time to get tough if
a vendor is dragging his feet, and maybe you will even have to make a switch...
but remember, too, that the grass will appear greener on the other side...

-------------------------------------------------------------------
     .     ..                    ..                
     .      .            .        .       Kevin R. Clark
    . .    .             .       .        Alcatel  Network Systems
    . .    .   ..   ... ...  ..  .        Dallas, Texas
   .  .    .  . .  .  .  .  . .  .            
   .....  .  .    .  .  .  ...  .         Work Phone: 214.996.2878
  .    .  .  .  . .  .  .  .  . .         Fax:        214.996.7362

-------------------------------------------------------------------



Tue, 15 Apr 1997 21:26:23 GMT  
 VHDL and VIEWLOGIC

Quote:
(Michael Smith) writes:

We've used the ViewLogic environment for quite a few years, and we
despise it thoroughly.  Their synthesizer is horrible (although its
probably acceptable if you are only going up to 10MHz or so) and their
own VHDL is incredibly limited (...WHAT...? I can't use a GENERATE
statement...!!!!  If I assign different bits of a bus from different
processes the entire bus goes 'X'...?  What's with this 'VLBIT' stuff?
You don't support std_logic....?  Yuck)

-- The interpretive VHDL was OK for what it did, but clearly 1076 was
needed- besides everybody tried to redefine VHDL constructs before 1076
became def facto AND de jure standard (unlike EDIF). Synthesis is
evolving, but is realistically not' there' yet; no big argument here,
although I have customers who are using the tool for FPGAs, a more
realistic target- as well as those who've rejected Synopsys for ASICs. Go
figure..

They have lots of glitzy literature, lots of GUI on-line documentation
etc., (where the useful features are un-documented) but no substance
for an ASIC engineer.  It looks like they tried to retrofit an ASIC
digital package onto a schematic capture/PCB package.  The result is a
huge mess.

Unfortunately, ViewLogic is buying all sorts of companies and
re-marketing their products as their own (for example, the Vantage
VHDL compiler is now badly integrated into the ViewLogic VHDL).
Hopefully the bad ViewLogic quality won't destroy products that
they now own that are actually useful (Motive, Vantage, etc.)

--Define 'badly'- is greater ease of use a 'bad' integration ? Is
incorporation of VHDL, Verilog and Viewsim models (and analog, for that
matter) a 'bad' integration ? As for buying companies, we see a
significant and positive impact to integrating these tools to play
together or separately. So do ***most** of our customers. I won't claim
that View quality is as good as it should be, but we are *ahead* of the
CAE vendors (not my words, my common customers'...)

We're getting away from it as fast as we can convert our files over to
something else.  We've switched to Vantage (20 times faster, although
unfortunately ViewLogic now owns them) for our simulation and Synopsys
for synthesis.

Please reconsider your decision to use ViewLogic, you'll hate yourself
for getting stuck with them once you see what the alternatives are.

---BS. Do use your head in making a decision & consider the alternatives.
I'm quite sorry that this fellow has a problem with our tools, but no one
claims absolute perfection in CAE, and if they do they are less that
honest...
Besides, could the 20-30% growth rate we're seeing be the result of smoke
and mirrors ? No...I'd say it's from companies who DID consider the
alternatives...

                                 -A.D. Stone - AE-SF Peninsula, Viewlogic



Tue, 15 Apr 1997 09:13:09 GMT  
 VHDL and VIEWLOGIC
Why dont you ask Viewlogic to supply details of reference sites that you
can talk to before making a decision.  That should not be too difficult
or time consuming.

Regards

Fred Jackson



Fri, 18 Apr 1997 05:38:03 GMT  
 VHDL and VIEWLOGIC

writes:

I have to disagree with you... Viewlogic tools are great!  All of them!

(Just my opinion)

JCaramani



Mon, 12 May 1997 13:10:15 GMT  
 
 [ 9 post ] 

 Relevant Pages 

1. VHDL and VIEWLOGIC

2. vhdl and viewlogic problem

3. VHDL and VIEWLOGIC

4. VHDL and VIEWLOGIC

5. Help needed for VHDL from VIEWLogic

6. vhdl viewlogic-specific function

7. VHDL models of Viewlogic primatives

8. Xilinx ViewLogic package and simulating VHDL

9. RE : Signal Attributes in Viewlogic VHDL

10. Synthesizer Bug? ViewLogic, VHDL, and XC4000

11. Open Collector o/p in ViewLogic VHDL

12. Viewlogic VHDL for Xilinx

 

 
Powered by phpBB® Forum Software