LeonardoSpectrum for Altera, VHDL -> EDIF conversion 
Author Message
 LeonardoSpectrum for Altera, VHDL -> EDIF conversion

Hi all;

I am a beginner of VHDL language.
Using LeonardoSpectrum for Altera (v2002a.14_OEM_Altera), I converted
two VHDL files which seems to be logically identical to EDIF files.
As you see the attached files, the circuit is a simple set reset
latch.
And I simulated them using MAX+Plus2. But the outputs are different.
And I think the second one (sr2.scf) is wrong.
Is this Leonardo's bug? Why does this happen?
"Warning : Design contains combinatorial loop through net unknown."
in the log made any effect to the simulation result, although
the same message also appears at compiling sr1.vhd?
How should I fix to get rid of this message?

Thanks in advance,
mips.

-------- sr1.scf -----------
s  LLLLLHHHHHLLLLLHHHHHLLLLL
r  HHHHHHHHHHLLLLLLLLLLLLLLL
q  HHHHHHHHHHHHHHHHLLLLLHHHH
qx LLLLLLLLLLLHHHHHHHHHHHHHH

-------- sr2.scf -----------
s  LLLLLHHHHHLLLLLHHHHHLLLLL
r  HHHHHHHHHHLLLLLLLLLLLLLLL
q  HHHHHHLLLLLHHHHHLLLLLHHHH  <-- here
qx LLLLLLLLLLLHHHHHHHHHHHHHH

-------- sr1.vhd -----------
library ieee;
use ieee.std_logic_1164.all;

entity sr is port(
    signal s, r:        in std_logic;
    signal q, qx:       buffer std_logic
);
end sr;

architecture behavior of sr is
begin
    q <= s nand qx;
    qx <= r nand q;
end behavior;

-------- sr2.vhd -----------
library ieee;
use ieee.std_logic_1164.all;

entity sr is port(
    signal s, r:        in std_logic;
    signal q, qx:       buffer std_logic
);
end sr;

architecture behavior of sr is
begin
    q <= not (s and qx);
    qx <= not (r and q);
end behavior;

------------ log at compiling sr2.vhd ---------
--
-- Welcome to LeonardoSpectrum for Altera
-- Run Started On Thu May 16 15:31:57 PST 2002
--
Info, Working Directory is now 'C:/xxx/altera/sr2'
->restore_project_script C:/xxx/sr2/sr2.scr
Reading library file
`C:\EXEMPLAR\LEOSPEC\OEM2002A_ALTERA_NIGHTLY_14\\lib\max7.syn`...
Library version = 1.1
Delays assume: Process=10
-- Reading module generator description from file
C:\EXEMPLAR\LEOSPEC\OEM2002A_ALTERA_NIGHTLY_14\\data\modgen\max7.vhd
-- Reading vhdl file
C:\EXEMPLAR\LEOSPEC\OEM2002A_ALTERA_NIGHTLY_14\\data\modgen\max7.vhd
into library OPERATORS
-- Modgen File max7.vhd Version 4.4
-- Reading file C:/xxx/sr2/sr2.xdb
-- Reading XDB version 1999.1
->set part EPM7032TC44
EPM7032TC44
->set process 10
10
->set max_fanin ""
->set lut_max_fanout ""
->set max_pt ""
->_gc_read_init
->_gc_run_init
->set input_file_list { C:/xxx/altera/sr2/sr2.vhd }
 C:/xxx/altera/sr2/sr2.vhd
->set encoding Auto
Auto
->set sdf_hierarchical_names FALSE
FALSE
->set sdf_type typical
typical
->set chip TRUE
->set macro FALSE
FALSE
->set optimize_for area
area
->set report brief
brief
->set -hierarchy auto
auto
->set hierarchy_auto TRUE
TRUE
->set hierarchy_preserve FALSE
FALSE
->set hierarchy_flatten FALSE
FALSE
->set output_file C:/xxx/altera/sr2/sr2.edf
C:/xxx/altera/sr2/sr2.edf
->set novendor_constraint_file FALSE
FALSE
->set target max7
max7
->_gc_read
-- Reading target technology max7
Reading library file
`C:\EXEMPLAR\LEOSPEC\OEM2002A_ALTERA_NIGHTLY_14\\lib\max7.syn`...
Library version = 1.1
Delays assume: Process=10
-- Reading module generator description from file
C:\EXEMPLAR\LEOSPEC\OEM2002A_ALTERA_NIGHTLY_14\\data\modgen\max7.vhd
-- Reading vhdl file
C:\EXEMPLAR\LEOSPEC\OEM2002A_ALTERA_NIGHTLY_14\\data\modgen\max7.vhd
into library OPERATORS
-- Modgen File max7.vhd Version 4.4
-- read -tech max7 { C:/xxx/altera/sr2/sr2.vhd }
-- Reading vhdl file C:/xxx/altera/sr2/sr2.vhd into library work
-- Loading entity sr into library work
-- Loading architecture behavior of sr into library work
-- Compiling root entity sr(behavior)
-- Pre Optimizing Design .work.sr.behavior
-- Boundary optimization.
Info: Finished reading design
->_gc_run
-- Run Started On Thu May 16 15:32:45 PST 2002
--
-- optimize -target max7 -effort quick -chip -area -hierarchy=auto
-- Start optimization for design .work.sr.behavior
Warning : Design contains combinatorial loop through net unknown.
Warning : Design contains combinatorial loop through net unknown.
Warning : Design contains combinatorial loop through net unknown.
Warning : Design contains combinatorial loop through net unknown.
              est est                                      
      Pass    LCs Delay EXPs DFFs TRIs  PIs POs    --CPU--
                                                     min:sec
      1         2     24   0     0    0    2   2      00:00
-- Start timing optimization for design .work.sr.behavior
Timing Optimization not supported for max7 technology.
*******************************************************
*******************************************************
Cell: sr    View: behavior    Library: work
Cell: sr    View: behavior    Library: work
*******************************************************
*******************************************************

 Number of ports :                       4
 Number of nets :                       14
 Number of instances :                  12
 Number of references to this view :     0

Total accumulated area :
 Number of LCs :                         2
 Number of accumulated instances :      12
***********************************************
Device Utilization for EPM7032TC44
***********************************************
Resource                Used    Avail   Utilization
-----------------------------------------------
IOs                     4       32       12.50%
LCs                     2       32        6.25%
DFFs                    0       32        0.00%
EXPs                    0       32        0.00%
-----------------------------------------------
-- Design summary in file 'C:/xxx/altera/sr2/sr2.sum'
-- Saving the design database in C:/xxx/altera/sr2/sr2.xdb
-- Writing file C:/xxx/altera/sr2/sr2.xdb
-- Writing XDB version 1999.1
-- Applying renaming rule 'ALTERA' to database
Warning, Renaming will cause your database to change
-- write C:/xxx/altera/sr2/sr2.edf
-- Writing file C:/xxx/altera/sr2/sr2.edf
Info, About to call 'setacf' for generating/modifying ACF file
Info, 'setacf' done.
-- CPU time taken for this run was  5.44 sec
-- Run Successfully Ended On  Thu May 16 15:32:50 PST 2002
0
Info: Finished Synthesis run



Mon, 01 Nov 2004 15:00:26 GMT  
 LeonardoSpectrum for Altera, VHDL -> EDIF conversion
Combinatorial feedback circuits require great care.  If you must, I would
really discourage building them behaviorally.  What you are seeing is
probably the result of the optimizer.  If you build a netlist in LAB's /
CLB's etc. you can get around this, and control exactly what you end up
with.  But, can't you get what you want out of either FF's or latches
provided in your target?  The timing will be much better than gates wired
together in a feedback loop.

Regards,


Quote:
> Hi all;

> I am a beginner of VHDL language.
> Using LeonardoSpectrum for Altera (v2002a.14_OEM_Altera), I converted
> two VHDL files which seems to be logically identical to EDIF files.
> As you see the attached files, the circuit is a simple set reset
> latch.
> And I simulated them using MAX+Plus2. But the outputs are different.
> And I think the second one (sr2.scf) is wrong.
> Is this Leonardo's bug? Why does this happen?
> "Warning : Design contains combinatorial loop through net unknown."
> in the log made any effect to the simulation result, although
> the same message also appears at compiling sr1.vhd?
> How should I fix to get rid of this message?

> Thanks in advance,
> mips.

> -------- sr1.scf -----------
> s  LLLLLHHHHHLLLLLHHHHHLLLLL
> r  HHHHHHHHHHLLLLLLLLLLLLLLL
> q  HHHHHHHHHHHHHHHHLLLLLHHHH
> qx LLLLLLLLLLLHHHHHHHHHHHHHH

> -------- sr2.scf -----------
> s  LLLLLHHHHHLLLLLHHHHHLLLLL
> r  HHHHHHHHHHLLLLLLLLLLLLLLL
> q  HHHHHHLLLLLHHHHHLLLLLHHHH  <-- here
> qx LLLLLLLLLLLHHHHHHHHHHHHHH

> -------- sr1.vhd -----------
> library ieee;
> use ieee.std_logic_1164.all;

> entity sr is port(
>     signal s, r: in std_logic;
>     signal q, qx: buffer std_logic
> );
> end sr;

> architecture behavior of sr is
> begin
>     q <= s nand qx;
>     qx <= r nand q;
> end behavior;

> -------- sr2.vhd -----------
> library ieee;
> use ieee.std_logic_1164.all;

> entity sr is port(
>     signal s, r: in std_logic;
>     signal q, qx: buffer std_logic
> );
> end sr;

> architecture behavior of sr is
> begin
>     q <= not (s and qx);
>     qx <= not (r and q);
> end behavior;

> ------------ log at compiling sr2.vhd ---------
> --
> -- Welcome to LeonardoSpectrum for Altera
> -- Run Started On Thu May 16 15:31:57 PST 2002
> --
> Info, Working Directory is now 'C:/xxx/altera/sr2'
> ->restore_project_script C:/xxx/sr2/sr2.scr
> Reading library file
> `C:\EXEMPLAR\LEOSPEC\OEM2002A_ALTERA_NIGHTLY_14\\lib\max7.syn`...
> Library version = 1.1
> Delays assume: Process=10
> -- Reading module generator description from file
> C:\EXEMPLAR\LEOSPEC\OEM2002A_ALTERA_NIGHTLY_14\\data\modgen\max7.vhd
> -- Reading vhdl file
> C:\EXEMPLAR\LEOSPEC\OEM2002A_ALTERA_NIGHTLY_14\\data\modgen\max7.vhd
> into library OPERATORS
> -- Modgen File max7.vhd Version 4.4
> -- Reading file C:/xxx/sr2/sr2.xdb
> -- Reading XDB version 1999.1
> ->set part EPM7032TC44
> EPM7032TC44
> ->set process 10
> 10
> ->set max_fanin ""
> ->set lut_max_fanout ""
> ->set max_pt ""
> ->_gc_read_init
> ->_gc_run_init
> ->set input_file_list { C:/xxx/altera/sr2/sr2.vhd }
>  C:/xxx/altera/sr2/sr2.vhd
> ->set encoding Auto
> Auto
> ->set sdf_hierarchical_names FALSE
> FALSE
> ->set sdf_type typical
> typical
> ->set chip TRUE
> ->set macro FALSE
> FALSE
> ->set optimize_for area
> area
> ->set report brief
> brief
> ->set -hierarchy auto
> auto
> ->set hierarchy_auto TRUE
> TRUE
> ->set hierarchy_preserve FALSE
> FALSE
> ->set hierarchy_flatten FALSE
> FALSE
> ->set output_file C:/xxx/altera/sr2/sr2.edf
> C:/xxx/altera/sr2/sr2.edf
> ->set novendor_constraint_file FALSE
> FALSE
> ->set target max7
> max7
> ->_gc_read
> -- Reading target technology max7
> Reading library file
> `C:\EXEMPLAR\LEOSPEC\OEM2002A_ALTERA_NIGHTLY_14\\lib\max7.syn`...
> Library version = 1.1
> Delays assume: Process=10
> -- Reading module generator description from file
> C:\EXEMPLAR\LEOSPEC\OEM2002A_ALTERA_NIGHTLY_14\\data\modgen\max7.vhd
> -- Reading vhdl file
> C:\EXEMPLAR\LEOSPEC\OEM2002A_ALTERA_NIGHTLY_14\\data\modgen\max7.vhd
> into library OPERATORS
> -- Modgen File max7.vhd Version 4.4
> -- read -tech max7 { C:/xxx/altera/sr2/sr2.vhd }
> -- Reading vhdl file C:/xxx/altera/sr2/sr2.vhd into library work
> -- Loading entity sr into library work
> -- Loading architecture behavior of sr into library work
> -- Compiling root entity sr(behavior)
> -- Pre Optimizing Design .work.sr.behavior
> -- Boundary optimization.
> Info: Finished reading design
> ->_gc_run
> -- Run Started On Thu May 16 15:32:45 PST 2002
> --
> -- optimize -target max7 -effort quick -chip -area -hierarchy=auto
> -- Start optimization for design .work.sr.behavior
> Warning : Design contains combinatorial loop through net unknown.
> Warning : Design contains combinatorial loop through net unknown.
> Warning : Design contains combinatorial loop through net unknown.
> Warning : Design contains combinatorial loop through net unknown.
>               est est
>       Pass    LCs Delay EXPs DFFs TRIs  PIs POs    --CPU--
>                                                      min:sec
>       1         2     24   0     0    0    2   2      00:00
> -- Start timing optimization for design .work.sr.behavior
> Timing Optimization not supported for max7 technology.
> *******************************************************
> *******************************************************
> Cell: sr    View: behavior    Library: work
> Cell: sr    View: behavior    Library: work
> *******************************************************
> *******************************************************

>  Number of ports :                       4
>  Number of nets :                       14
>  Number of instances :                  12
>  Number of references to this view :     0

> Total accumulated area :
>  Number of LCs :                         2
>  Number of accumulated instances :      12
> ***********************************************
> Device Utilization for EPM7032TC44
> ***********************************************
> Resource                Used    Avail   Utilization
> -----------------------------------------------
> IOs                     4       32       12.50%
> LCs                     2       32        6.25%
> DFFs                    0       32        0.00%
> EXPs                    0       32        0.00%
> -----------------------------------------------
> -- Design summary in file 'C:/xxx/altera/sr2/sr2.sum'
> -- Saving the design database in C:/xxx/altera/sr2/sr2.xdb
> -- Writing file C:/xxx/altera/sr2/sr2.xdb
> -- Writing XDB version 1999.1
> -- Applying renaming rule 'ALTERA' to database
> Warning, Renaming will cause your database to change
> -- write C:/xxx/altera/sr2/sr2.edf
> -- Writing file C:/xxx/altera/sr2/sr2.edf
> Info, About to call 'setacf' for generating/modifying ACF file
> Info, 'setacf' done.
> -- CPU time taken for this run was  5.44 sec
> -- Run Successfully Ended On  Thu May 16 15:32:50 PST 2002
> 0
> Info: Finished Synthesis run



Mon, 01 Nov 2004 20:12:52 GMT  
 
 [ 2 post ] 

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