need help in byte stuffing vhdl code
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leir #1 / 6
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need help in byte stuffing vhdl code
Hello, Im working writing the vhdl code for a ppp packet processor. There some of dta bytes must be stuffed, so input data has to be outputed in one of these ways: 1. out byte is the same as in byte 2. out byte is the flag byte followed by a stuffed byte. I have tried a lot of things, can you help me with this? I post here my last program that gives failures while simulation: LIBRARY ieee; USE ieee.std_logic_1164.all; ENTITY fifo0 IS -- {{ALTERA_IO_BEGIN}} DO NOT REMOVE THIS LINE! PORT ( clk : IN STD_LOGIC; datos : IN STD_LOGIC_VECTOR(7 downto 0); datos_f : OUT STD_LOGIC_VECTOR(7 downto 0); datfifo : OUT STD_LOGIC_VECTOR(7 downto 0) ); -- {{ALTERA_IO_END}} DO NOT REMOVE THIS LINE! END fifo0; ARCHITECTURE fifo0_architecture OF fifo0 IS CONSTANT flag: std_logic_vector(7 downto 0):="01111110";--7E ~ CONSTANT stuff: std_logic_vector(7 downto 0):="01011101";--5D ] CONSTANT veinte: std_logic_vector(7 downto 0):="00100000";--20 espacio SIGNAL cola: std_logic_vector(15 downto 0); TYPE estado1 IS (uno,dos,tres,cuatro,cinco,seis,siete,ocho,nueve,diez); TYPE estado2 IS (uno,unos,dos,doss,tres,tress,cuatro,cuatros,cinco,cincos,seis,seiss,siete,sietes,ocho,ochos,nueve,nueves,diez,diezs); SIGNAL cs1: estado1:=uno; SIGNAL cs2: estado2:=uno; BEGIN p2:process (clk) BEGIN if (clk'event and clk='1')then case cs1 is when uno=> cola(7 downto 0)<=datos; cs1<=dos; when dos=> cola(15 downto 8)<=datos; cs1<=tres; when tres=> cola(23 downto 16)<=datos; cs1<=cuatro; when cuatro=> cola(31 downto 24)<=datos; cs1<=cinco; when cinco=> cola(39 downto 32)<=datos; cs1<=seis; when seis=> cola(47 downto 40)<=datos; cs1<=siete; when siete=> cola(55 downto 48)<=datos; cs1<=ocho; when ocho=> cola(63 downto 56)<=datos; cs1<=nueve; when nueve=> cola(71 downto 64)<=datos; cs1<=diez; when diez=> cola(79 downto 72)<=datos; cs1<=uno; when others=> null; end case; end if; end process p2; p1:process (clk) BEGIN if (clk'event and clk='1')then case cs2 IS when uno=> if (cola(7 downto 0)=flag) then medio<=stuff;--] cs2<=unos; else medio<=cola(7 downto 0); cs2<=dos; end if; when unos=> medio<= cola(7 downto 0) xor veinte; cs2<=dos; when dos=> if (cola(15 downto 8)=flag) then medio<=stuff; cs2<=doss; else medio<=cola(15 downto 8); cs2<=tres; end if; when doss=> medio<=cola(15 downto 8) xor veinte; cs2<=tres; when tres=> if (cola(23 downto 16)=flag) then medio<=stuff;--] cs2<=tress; else medio<=cola(23 downto 16); cs2<=cuatro; end if; when tress=> medio<=cola(23 downto 16) xor veinte; cs2<=cuatro; when cuatro=> if (cola(31 downto 24)=flag) then medio<=stuff; cs2<=cuatros; else medio<=cola(31 downto 24); cs2<=cinco; end if; when cuatros=> medio<=cola(31 downto 24) xor veinte; cs2<=cinco; when cinco=> if (cola(39 downto 32)=flag) then medio<=stuff; cs2<=cincos; else medio<=cola(39 downto 32); cs2<=cincos; end if; when cincos=> medio<=cola(39 downto 32) xor veinte; cs2<=seis; when seis=> if (cola(47 downto 40)=flag) then medio<=stuff; cs2<=seiss; else medio<=cola(47 downto 40); cs2<=siete; end if; when seiss=> medio<=cola(47 downto 40) xor veinte; cs2<=siete; when siete=> if (cola(55 downto 48)=flag) then medio<=stuff; cs2<=sietes; else medio<=cola(55 downto 48); cs2<=ocho; end if; when sietes=> medio<=cola(55 downto 48) xor veinte; cs2<=ocho; when ocho=> if (cola(63 downto 56)=flag) then medio<=stuff; cs2<=ochos; else medio<=cola(63 downto 56); cs2<=nueve; end if; when ochos=> medio<=cola(63 downto 56) xor veinte; cs2<=nueve; when nueve=> if (cola(71 downto 64)=flag) then medio<=stuff; cs2<=nueves; else medio<=cola(71 downto 64); cs2<=diez; end if; when nueves=> medio<=cola(71 downto 64) xor veinte; cs2<=diez; when diez=> if (cola(79 downto 72)=flag) then medio<=stuff; cs2<=diezs; else medio<=cola(79 downto 72); cs2<=uno; end if; when diezs=> medio<=cola(79 downto 72) xor veinte; cs2<=uno; when others=> null; end case; end if; end process p1; datos_f<=medio; END fifo0_architecture; thanks a lot, leire
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Mon, 16 May 2005 19:17:03 GMT |
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Srinivasan Venkataramana #2 / 6
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need help in byte stuffing vhdl code
Hi Leire,
Quote: > Hello, Im working writing the vhdl code for a ppp packet processor. > There some of dta bytes must be stuffed, so input data has to be > outputed in one of these ways: > 1. out byte is the same as in byte > 2. out byte is the flag byte followed by a stuffed byte. > I have tried a lot of things, can you help me with this? I post here > my last program that gives failures while simulation:
It may be useful (for us to get a quicker feel of your problem, and suggest a solution) if you can explain what sort of failure you see in detail. Honestly I haven't yet read through the long code that you posted. <SNIP> Good Luck, Srinivasan -- Srinivasan Venkataramanan ASIC Design Engineer Software & Silicon Systems India Pvt Ltd. - an Intel company Bangalore, India I don't speak for Intel
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Tue, 17 May 2005 14:17:56 GMT |
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leir #3 / 6
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need help in byte stuffing vhdl code
Quote:
> Hello, Im working writing the vhdl code for a ppp packet processor. > There some of dta bytes must be stuffed, so input data has to be > outputed in one of these ways: > 1. out byte is the same as in byte > 2. out byte is the flag byte followed by a stuffed byte. > I have tried a lot of things, can you help me with this? I post here > my last program that gives failures while simulation: > LIBRARY ieee; > USE ieee.std_logic_1164.all; > ENTITY fifo0 IS > -- {{ALTERA_IO_BEGIN}} DO NOT REMOVE THIS LINE! > PORT > ( > clk : IN STD_LOGIC; > datos : IN STD_LOGIC_VECTOR(7 downto 0); > datos_f : OUT STD_LOGIC_VECTOR(7 downto 0); > datfifo : OUT STD_LOGIC_VECTOR(7 downto 0) > ); > -- {{ALTERA_IO_END}} DO NOT REMOVE THIS LINE! > END fifo0; > ARCHITECTURE fifo0_architecture OF fifo0 IS > CONSTANT flag: std_logic_vector(7 downto 0):="01111110";--7E ~ > CONSTANT stuff: std_logic_vector(7 downto 0):="01011101";--5D ] > CONSTANT veinte: std_logic_vector(7 downto 0):="00100000";--20 > espacio > SIGNAL cola: std_logic_vector(15 downto 0); > TYPE estado1 IS (uno,dos,tres,cuatro,cinco,seis,siete,ocho,nueve,diez); > TYPE estado2 IS (uno,unos,dos,doss,tres,tress,cuatro,cuatros,cinco,cincos,seis,seiss,siete,sietes,ocho,ochos,nueve,nueves,diez,diezs); > SIGNAL cs1: estado1:=uno; > SIGNAL cs2: estado2:=uno; > BEGIN > p2:process (clk) > BEGIN > if (clk'event and clk='1')then > case cs1 is > when uno=> > cola(7 downto 0)<=datos; > cs1<=dos; > when dos=> > cola(15 downto 8)<=datos; > cs1<=tres; > when tres=> > cola(23 downto 16)<=datos; > cs1<=cuatro; > when cuatro=> > cola(31 downto 24)<=datos; > cs1<=cinco; > when cinco=> > cola(39 downto 32)<=datos; > cs1<=seis; > when seis=> > cola(47 downto 40)<=datos; > cs1<=siete; > when siete=> > cola(55 downto 48)<=datos; > cs1<=ocho; > when ocho=> > cola(63 downto 56)<=datos; > cs1<=nueve; > when nueve=> > cola(71 downto 64)<=datos; > cs1<=diez; > when diez=> > cola(79 downto 72)<=datos; > cs1<=uno; > when others=> > null; > end case; > end if; > end process p2; > p1:process (clk) > BEGIN > if (clk'event and clk='1')then > case cs2 IS > when uno=> > if (cola(7 downto 0)=flag) then > medio<=stuff;--] > cs2<=unos; > else > medio<=cola(7 downto 0); > cs2<=dos; > end if; > when unos=> > medio<= cola(7 downto 0) xor veinte; > cs2<=dos; > when dos=> > if (cola(15 downto 8)=flag) then > medio<=stuff; > cs2<=doss; > else > medio<=cola(15 downto 8); > cs2<=tres; > end if; > when doss=> > medio<=cola(15 downto 8) xor veinte; > cs2<=tres; > when tres=> > if (cola(23 downto 16)=flag) then > medio<=stuff;--] > cs2<=tress; > else > medio<=cola(23 downto 16); > cs2<=cuatro; > end if; > when tress=> > medio<=cola(23 downto 16) xor veinte; > cs2<=cuatro; > when cuatro=> > if (cola(31 downto 24)=flag) then > medio<=stuff; > cs2<=cuatros; > else > medio<=cola(31 downto 24); > cs2<=cinco; > end if; > when cuatros=> > medio<=cola(31 downto 24) xor veinte; > cs2<=cinco; > when cinco=> > if (cola(39 downto 32)=flag) then > medio<=stuff; > cs2<=cincos; > else > medio<=cola(39 downto 32); > cs2<=cincos; > end if; > when cincos=> > medio<=cola(39 downto 32) xor veinte; > cs2<=seis; > when seis=> > if (cola(47 downto 40)=flag) then > medio<=stuff; > cs2<=seiss; > else > medio<=cola(47 downto 40); > cs2<=siete; > end if; > when seiss=> > medio<=cola(47 downto 40) xor veinte; > cs2<=siete; > when siete=> > if (cola(55 downto 48)=flag) then > medio<=stuff; > cs2<=sietes; > else > medio<=cola(55 downto 48); > cs2<=ocho; > end if; > when sietes=> > medio<=cola(55 downto 48) xor veinte; > cs2<=ocho; > when ocho=> > if (cola(63 downto 56)=flag) then > medio<=stuff; > cs2<=ochos; > else > medio<=cola(63 downto 56); > cs2<=nueve; > end if; > when ochos=> > medio<=cola(63 downto 56) xor veinte; > cs2<=nueve; > when nueve=> > if (cola(71 downto 64)=flag) then > medio<=stuff; > cs2<=nueves; > else > medio<=cola(71 downto 64); > cs2<=diez; > end if; > when nueves=> > medio<=cola(71 downto 64) xor veinte; > cs2<=diez; > when diez=> > if (cola(79 downto 72)=flag) then > medio<=stuff; > cs2<=diezs; > else > medio<=cola(79 downto 72); > cs2<=uno; > end if; > when diezs=> > medio<=cola(79 downto 72) xor veinte; > cs2<=uno; > when others=> > null; > end case; > end if; > end process p1; > datos_f<=medio; > END fifo0_architecture; > thanks a lot, leire
Its because I use a signal of 8 bytes as a buffer, so when i want to take out one value i cant access to only one byte of this signal. I dont know if the problem is with my code or with alteras simulator or compiler for quartus II, and because I havent money to purchase leonardo spectrum and modelsim i have to think about another way to do it to continue designing a ppp packet processor. although the code may be correct if i cant simulate it well it has no use for me. I thought of using a fifo whith pointers, but in my blocks the byte arrives as a std_logic_vector and arrays are of type char so i couldnt assign a std_logic_vector to a char. thanks a lot, leire
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Tue, 17 May 2005 15:57:40 GMT |
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leir #4 / 6
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need help in byte stuffing vhdl code
I have added some comments to the progam, but i would like you to give me different program alternatives that can be improvements in this or completely different. Now I havent a start/stop flag but when i test well this part i will put one thans, leire LIBRARY ieee; USE ieee.std_logic_1164.all; -- Entity Declaration ENTITY fifo0 IS -- {{ALTERA_IO_BEGIN}} DO NOT REMOVE THIS LINE! PORT ( clk : IN STD_LOGIC; datos : IN STD_LOGIC_VECTOR(7 downto 0); datos_f : OUT STD_LOGIC_VECTOR(7 downto 0) ); -- {{ALTERA_IO_END}} DO NOT REMOVE THIS LINE! END fifo0; -- Architecture Body ARCHITECTURE fifo0_architecture OF fifo0 IS CONSTANT flag: std_logic_vector(7 downto 0):="01111110";--7E ~ CONSTANT stuff: std_logic_vector(7 downto 0):="01011101";--5D ] CONSTANT veinte: std_logic_vector(7 downto 0):="00100000";--20 espacio -- 'fifo' is implemented with a 80 bit signal -- divided into 10 signals of 8 bit SIGNAL cola: std_logic_vector(79 downto 0); TYPE estado1 IS (uno,dos,tres,cuatro,cinco,seis,siete,ocho,nueve,diez); TYPE estado2 IS (uno,unos,dos,doss,tres,tress,cuatro,cuatros,cinco,cincos,seis,seiss,siete,s ietes,ocho,ochos,nueve,nueves,diez,diezs); SIGNAL cs1: estado1:=uno; SIGNAL cs2: estado2:=uno; SIGNAL medio: std_logic_vector(7 downto 0); BEGIN p2:process (clk) BEGIN if (clk'event and clk='1')then --each clock event bytes received are kept --in a 'cola' called signal with a 8 bit space difference between them case cs1 is when uno=> cola(7 downto 0)<=datos; cs1<=dos; when dos=> cola(15 downto 8)<=datos; cs1<=tres; when tres=> cola(23 downto 16)<=datos; cs1<=cuatro; when cuatro=> cola(31 downto 24)<=datos; cs1<=cinco; when cinco=> cola(39 downto 32)<=datos; cs1<=seis; when seis=> cola(47 downto 40)<=datos; cs1<=siete; when siete=> cola(55 downto 48)<=datos; cs1<=ocho; when ocho=> cola(63 downto 56)<=datos; cs1<=nueve; when nueve=> cola(71 downto 64)<=datos; cs1<=diez; when diez=> cola(79 downto 72)<=datos; cs1<=uno; when others=> null; end case; end if; end process p2; p1:process (clk) BEGIN if (clk'event and clk='1')then case cs2 IS when uno=> --if the data that is in those first 8 bit --(part of the 80 bit signal) is a flag --stuff byte is outputed --and we go to a special state: unos if (cola(7 downto 0)=flag) then medio<=stuff;--] cs2<=unos; else -- if data isnt a flag we output it and go to the --next normal state medio<=cola(7 downto 0); cs2<=dos; end if; when unos=> -- we stay in the same first 8 bits -- and output them but a bit changed --and go to the next normal state medio<= cola(7 downto 0) xor veinte; cs2<=dos; when dos=> if (cola(15 downto 8)=flag) then medio<=stuff; cs2<=doss; else medio<=cola(15 downto 8); cs2<=tres; end if; when doss=> medio<=cola(15 downto 8) xor veinte; cs2<=tres; when tres=> if (cola(23 downto 16)=flag) then medio<=stuff;--] cs2<=tress; else medio<=cola(23 downto 16); cs2<=cuatro; end if; when tress=> medio<=cola(23 downto 16) xor veinte; cs2<=cuatro; when cuatro=> if (cola(31 downto 24)=flag) then medio<=stuff; cs2<=cuatros; else medio<=cola(31 downto 24); cs2<=cinco; end if; when cuatros=> medio<=cola(31 downto 24) xor veinte; cs2<=cinco; when cinco=> if (cola(39 downto 32)=flag) then medio<=stuff; cs2<=cincos; else medio<=cola(39 downto 32); cs2<=cincos; end if; when cincos=> medio<=cola(39 downto 32) xor veinte; cs2<=seis; when seis=> if (cola(47 downto 40)=flag) then medio<=stuff; cs2<=seiss; else medio<=cola(47 downto 40); cs2<=siete; end if; when seiss=> medio<=cola(47 downto 40) xor veinte; cs2<=siete; when siete=> if (cola(55 downto 48)=flag) then medio<=stuff; cs2<=sietes; else medio<=cola(55 downto 48); cs2<=ocho; end if; when sietes=> medio<=cola(55 downto 48) xor veinte; cs2<=ocho; when ocho=> if (cola(63 downto 56)=flag) then medio<=stuff; cs2<=ochos; else medio<=cola(63 downto 56); cs2<=nueve; end if; when ochos=> medio<=cola(63 downto 56) xor veinte; cs2<=nueve; when nueve=> if (cola(71 downto 64)=flag) then medio<=stuff; cs2<=nueves; else medio<=cola(71 downto 64); cs2<=diez; end if; when nueves=> medio<=cola(71 downto 64) xor veinte; cs2<=diez; when diez=> if (cola(79 downto 72)=flag) then medio<=stuff; cs2<=diezs; else medio<=cola(79 downto 72); cs2<=uno; end if; when diezs=> medio<=cola(79 downto 72) xor veinte; cs2<=uno; when others=> null; end case; end if; end process p1; datos_f<=medio; END fifo0_architecture;
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Tue, 17 May 2005 21:39:06 GMT |
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Egbert Molenkam #5 / 6
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need help in byte stuffing vhdl code
Quote: > Its because I use a signal of 8 bytes as a buffer, so when i want to > take out one value i cant access to only one byte of this signal. I > dont know if the problem is with my code or with alteras simulator > or compiler for quartus II, and because I havent money to purchase > leonardo spectrum and modelsim i have to think about another way to do > it to continue designing a ppp packet processor. although the code may > be correct if i cant simulate it well it has no use for me. I thought > of using a fifo whith pointers, but in my blocks the byte arrives as a > std_logic_vector and arrays are of type char so i couldnt assign a > std_logic_vector to a char.
If you use Altera can you get for free a Leonardo front end? (see the altera website). I had a look at your code. In fact it looks very regular. Two processes. One process subsequently write the next byte on the next position in the 80 bits cola. The read process is a little biut more complicated, but still regular. In a state i it checks wether: the pattern is a flag => then it generates a stuff byte and in the clock period an exor operation with the data is performed with flag otherwise the data in cola is going to the output. With this in mind. I tried to make use of the regular structure. Here my first attemp (no guarentee, no simulation performed etc.) After this you find a synthesisable solution. But first the straighforward one: LIBRARY ieee; USE ieee.std_logic_1164.all; -- Entity Declaration ENTITY fifo0 IS -- {{ALTERA_IO_BEGIN}} DO NOT REMOVE THIS LINE! PORT (reset : IN std_logic; clk : IN STD_LOGIC; datos : IN STD_LOGIC_VECTOR(7 downto 0); datos_f : OUT STD_LOGIC_VECTOR(7 downto 0) ); -- {{ALTERA_IO_END}} DO NOT REMOVE THIS LINE! END fifo0; -- Architecture Body ARCHITECTURE fifo0_architecture OF fifo0 IS CONSTANT flag: std_logic_vector(7 downto 0):="01111110";--7E ~ CONSTANT stuff: std_logic_vector(7 downto 0):="01011101";--5D ] CONSTANT veinte: std_logic_vector(7 downto 0):="00100000";--20 espacio -- 'fifo' is implemented with a 80 bit signal -- divided into 10 signals of 8 bit SIGNAL cola: std_logic_vector(79 downto 0); SIGNAL medio: std_logic_vector(7 downto 0); BEGIN p2:process (reset,clk) variable i : integer range 0 to 9; -- state BEGIN if reset='0' then i:=0; elsif clk'event and clk='1' then cola (8*(i+1)-1 downto 8*i) <= datos; if i<9 then i:=i+1; else i:=0; end if; end if; end process p2; process(reset,clk) variable i : integer range 0 to 10; variable flag_found : boolean; variable prev_data : std_logic_vector(7 downto 0); begin if reset='0' then i:=0; flag_found:=false; prev_data:= (others=>'0'); elsif clk'event and clk='1' then if flag_found then medio <= prev_data xor veinte; flag_found := false; elsif cola (8*(i+1)-1 downto 8*i)=flag then medio <= stuff; flag_found := true; prev_data := cola (8*(i+1)-1 downto 8*i); -- used in next clock period to xor with veinte else medio <= cola (8*(i+1)-1 downto 8*i); end if; if i<9 then i:=i+1; else i:=0; end if; end if; end process; datos_f<=medio; END fifo0_architecture; In fact only once the behaviour is worked out for a state. The index i is the state. In the read process an additional variable flag_found is used which is needed for the XOR with veinte. This is probably not synthesisable. Synthesis tools don't like: cola (8*(i+1)-1 downto 8*i) <= datos; if i is NOT a constant. However a trick to solve this problem is using a for loop. The index variable in a for loop is a constant! So the trick is: put a for loop around the code and check if the loop variable is equal with i (this will exactly occurs ones). Replace in the bode of the for loop the non constant i with the constant loop variable and since there was a check 'loop variable'=i the behaviour is unchanged. The synthesis tool I use needed 98 flipflops for a realisation. Remember that cola needs already 80 flipflops! As said before no guarantee (even not simulated!) but maybe it gives you a way how to solve it. Success. Egbert Molenkamp ARCHITECTURE fifo0_architecture OF fifo0 IS CONSTANT flag: std_logic_vector(7 downto 0):="01111110";--7E ~ CONSTANT stuff: std_logic_vector(7 downto 0):="01011101";--5D ] CONSTANT veinte: std_logic_vector(7 downto 0):="00100000";--20 espacio -- 'fifo' is implemented with a 80 bit signal -- divided into 10 signals of 8 bit SIGNAL cola: std_logic_vector(79 downto 0); SIGNAL medio: std_logic_vector(7 downto 0); BEGIN p2:process (reset,clk) variable i : integer range 0 to 9; -- state BEGIN if reset='0' then i:=0; cola <=(others=>'0'); elsif clk'event and clk='1' then for j in 0 to 9 loop --*** only to mislead synthesis tooling if j=i then --*** cola (8*(j+1)-1 downto 8*i) <= datos; -- i replaced with j end if; --*** end loop; --*** if i<9 then i:=i+1; else i:=0; end if; end if; end process p2; process(reset,clk) variable i : integer range 0 to 10; variable flag_found : boolean; variable prev_data : std_logic_vector(7 downto 0); begin if reset='0' then i:=0; flag_found:=false; prev_data:= (others=>'0'); elsif clk'event and clk='1' then for j in 0 to 9 loop --*** only to mislead synthesis tooling if j=i then --*** if flag_found then medio <= prev_data xor veinte; flag_found := false; elsif cola (8*(j+1)-1 downto 8*j)=flag then medio <= stuff; flag_found := true; prev_data := cola (8*(j+1)-1 downto 8*j); -- used in next clock period to xor with veinte else medio <= cola (8*(j+1)-1 downto 8*j); end if; end if; --** end loop; --** if i<9 then i:=i+1; else i:=0; end if; end if; end process; datos_f<=medio; END fifo0_architecture;
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Wed, 18 May 2005 00:15:16 GMT |
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Andre #6 / 6
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need help in byte stuffing vhdl code
Quote:
> > Its because I use a signal of 8 bytes as a buffer, so when i want to > > take out one value i cant access to only one byte of this signal. I > > dont know if the problem is with my code or with alteras simulator > > or compiler for quartus II, and because I havent money to purchase > > leonardo spectrum and modelsim i have to think about another way to do > > it to continue designing a ppp packet processor. although the code may > > be correct if i cant simulate it well it has no use for me. I thought > > of using a fifo whith pointers, but in my blocks the byte arrives as a > > std_logic_vector and arrays are of type char so i couldnt assign a > > std_logic_vector to a char. > If you use Altera can you get for free a Leonardo front end? (see the altera > website).
If you have Altera's licence you can use Modelsim-Altera 5.5 now.It's like Modelsim 5.5 ,but works with Altera's licence Quote: > I had a look at your code. In fact it looks very regular. Two processes. > One process subsequently write the next byte on the next position in the > 80 bits cola. > The read process is a little biut more complicated, but still regular. > In a state i it checks wether: > the pattern is a flag => then it generates a stuff byte and in the > clock period an exor operation with the data is performed with flag > otherwise the data in cola is going to the output. > With this in mind. I tried to make use of the regular structure. > Here my first attemp (no guarentee, no simulation performed etc.) > After this you find a synthesisable solution. > But first the straighforward one: > LIBRARY ieee; > USE ieee.std_logic_1164.all; > -- Entity Declaration > ENTITY fifo0 IS > -- {{ALTERA_IO_BEGIN}} DO NOT REMOVE THIS LINE! > PORT > (reset : IN std_logic; > clk : IN STD_LOGIC; > datos : IN STD_LOGIC_VECTOR(7 downto 0); > datos_f : OUT STD_LOGIC_VECTOR(7 downto 0) > ); > -- {{ALTERA_IO_END}} DO NOT REMOVE THIS LINE! > END fifo0; > -- Architecture Body > ARCHITECTURE fifo0_architecture OF fifo0 IS > CONSTANT flag: std_logic_vector(7 downto 0):="01111110";--7E ~ > CONSTANT stuff: std_logic_vector(7 downto 0):="01011101";--5D ] > CONSTANT veinte: std_logic_vector(7 downto 0):="00100000";--20 espacio > -- 'fifo' is implemented with a 80 bit signal > -- divided into 10 signals of 8 bit > SIGNAL cola: std_logic_vector(79 downto 0); > SIGNAL medio: std_logic_vector(7 downto 0); > BEGIN > p2:process (reset,clk) > variable i : integer range 0 to 9; -- state > BEGIN > if reset='0' then > i:=0; > elsif clk'event and clk='1' then > cola (8*(i+1)-1 downto 8*i) <= datos; > if i<9 then > i:=i+1; > else > i:=0; > end if; > end if; > end process p2; > process(reset,clk) > variable i : integer range 0 to 10; > variable flag_found : boolean; > variable prev_data : std_logic_vector(7 downto 0); > begin > if reset='0' then > i:=0; flag_found:=false; prev_data:= (others=>'0'); > elsif clk'event and clk='1' then > if flag_found then > medio <= prev_data xor veinte; > flag_found := false; > elsif cola (8*(i+1)-1 downto 8*i)=flag then > medio <= stuff; > flag_found := true; > prev_data := cola (8*(i+1)-1 downto 8*i); -- used in next clock period > to xor with veinte > else > medio <= cola (8*(i+1)-1 downto 8*i); > end if; > if i<9 then > i:=i+1; > else > i:=0; > end if; > end if; > end process; > datos_f<=medio; > END fifo0_architecture; > In fact only once the behaviour is worked out for a state. The index i is > the state. In the read process an additional variable flag_found is used > which is needed for the XOR with veinte. > This is probably not synthesisable. Synthesis tools don't like: > cola (8*(i+1)-1 downto 8*i) <= datos; > if i is NOT a constant. > However a trick to solve this problem is using a for loop. The index > variable > in a for loop is a constant! So the trick is: put a for loop around the code > and check if the loop variable is equal with i (this will exactly occurs > ones). > Replace in the bode of the for loop the non constant i with the constant > loop variable and since there was a check 'loop variable'=i the behaviour > is unchanged. > The synthesis tool I use needed 98 flipflops for a realisation. Remember > that cola needs already 80 flipflops! > As said before no guarantee (even not simulated!) but maybe it gives you a > way how to solve it. > Success. > Egbert Molenkamp > ARCHITECTURE fifo0_architecture OF fifo0 IS > CONSTANT flag: std_logic_vector(7 downto 0):="01111110";--7E ~ > CONSTANT stuff: std_logic_vector(7 downto 0):="01011101";--5D ] > CONSTANT veinte: std_logic_vector(7 downto 0):="00100000";--20 espacio > -- 'fifo' is implemented with a 80 bit signal > -- divided into 10 signals of 8 bit > SIGNAL cola: std_logic_vector(79 downto 0); > SIGNAL medio: std_logic_vector(7 downto 0); > BEGIN > p2:process (reset,clk) > variable i : integer range 0 to 9; -- state > BEGIN > if reset='0' then > i:=0; cola <=(others=>'0'); > elsif clk'event and clk='1' then > for j in 0 to 9 loop --*** only to mislead synthesis tooling > if j=i then --*** > cola (8*(j+1)-1 downto 8*i) <= datos; -- i replaced with j > end if; --*** > end loop; --*** > if i<9 then > i:=i+1; > else > i:=0; > end if; > end if; > end process p2; > process(reset,clk) > variable i : integer range 0 to 10; > variable flag_found : boolean; > variable prev_data : std_logic_vector(7 downto 0); > begin > if reset='0' then > i:=0; flag_found:=false; prev_data:= (others=>'0'); > elsif clk'event and clk='1' then > for j in 0 to 9 loop --*** only to mislead synthesis tooling > if j=i then --*** > if flag_found then > medio <= prev_data xor veinte; > flag_found := false; > elsif cola (8*(j+1)-1 downto 8*j)=flag then > medio <= stuff; > flag_found := true; > prev_data := cola (8*(j+1)-1 downto 8*j); -- used in next clock > period to xor with veinte > else > medio <= cola (8*(j+1)-1 downto 8*j); > end if; > end if; --** > end loop; --** > if i<9 then > i:=i+1; > else > i:=0; > end if; > end if; > end process; > datos_f<=medio; > END fifo0_architecture;
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Sat, 21 May 2005 17:27:33 GMT |
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