VHDL function declaration (variable) 
Author Message
 VHDL function declaration (variable)

Hi,

Can anyone tell me if there is anything wrong with the way I have
declared my function variables? I have declared variables of different
vector lengths (i.e. std_ulogic and std_ulogic_vector). I have also
declared op1 and op2 together with rdd1, rdd2, rss2, rtt2. They have
different vector lengths (i.e. op1 and op2 are 4 in length and rdd1,
rdd2, rss2, rtt2 are 3 in length ). If there are any suggestions to

code is as follows :

---------- start of function -------------

   function instr2_depends_on_instr1 (ex_mode : std_ulogic, op1, op2,
rdd1, rdd2, rss2, rtt2 : std_ulogic_vector ) return boolean is

   begin  -- instr2_depends_on_instr1 ( std_ulogic_vector )

 if op1 = end_1 or (op1 = rete or op1 = ecall) or (op1 = ret or op1 =
jal) or (op1 = jr or op1 = bltz) or (op1 = beqz or  op1 = sw) then

  return false ;

 elsif (op1 = movui and op2 = movli) or (op2 = movui and op1 = movli)
then

  if rdd1 = rdd2 then

   return true ;

  else

   return true ;

  end if ;

 else

  case op2 is

  when add|sub|mul|and_op|or_op|xor_op =>

   if rdd1(3) = ex_mode and (rss2 = rdd1 or rtt2 = rdd1) then

    return true ;

   else

    return false ;

   end if ;

  when mov =>

   if rdd1(3) = ex_mode and rss2 = rdd1 then

    return true ;

   else

    return false ;

   end if ;

  when sw|lw =>

   if rdd1(3) = ex_mode and (rtt2 = rdd1 or rdd2 = rdd1) then

    return true ;

   else

    return false ;

   end if ;

  when jr|bltz|beqz|movui|movli|shli|shri|sari|not_op =>

   if rdd1(3) = ex_mode and rtt2 = rdd1 then

    return true ;

   else

    return false ;

   end if ;

  when others =>

   return false ;

  end case ;

 end if ;

   end instr2_depends_on_instr1 ;

----------- end of function ----------------

Hern Lim



Sun, 01 Oct 2000 03:00:00 GMT  
 VHDL function declaration (variable)

Quote:

> Hi,

> Can anyone tell me if there is anything wrong with the way I have
> declared my function variables? I have declared variables of different
> vector lengths (i.e. std_ulogic and std_ulogic_vector). I have also
> declared op1 and op2 together with rdd1, rdd2, rss2, rtt2. They have
> different vector lengths (i.e. op1 and op2 are 4 in length and rdd1,
> rdd2, rss2, rtt2 are 3 in length ). If there are any suggestions to

> code is as follows :

> ---------- start of function -------------

>    function instr2_depends_on_instr1 (ex_mode : std_ulogic, op1, op2,
> rdd1, rdd2, rss2, rtt2 : std_ulogic_vector ) return boolean is

>    begin  -- instr2_depends_on_instr1 ( std_ulogic_vector )
> ...

The only obvious error is that after 'std_ulogic' there should be a
';' instead of ','.

It is possible to declare op1, ..., rtt2 with the
unconstrained type std_ulogic_vector. This, however, means that the
implementation of the function should work with vectors of any width
because the width of op1, ..., rtt2 depends on the width of the
actual parameters which are passed to the function when called. If
you know the length of these vectors when writing the function, it
might be better/easier to use a constrained type, e.g.
std_logic_vector(7 downto 0)

Also the parameters of the function are no variables. They are
(by use of default rules) declared as constants, and that's right
because parameters of functions must be constants or signals but
no variables, and they may only be read in the function. I think
that's what you want; however, if you need variables (e.g. for
output parameters), you could write a procedure instead (which of
course has no return value, but that could still be passed as an
output parameter).

Regards,
Martin

--
________________________________________________________________________
 Martin Radetzki                                Tel.: **49-441-798-2988
 OFFIS Research Institute                       Fax.: **49-441-798-2145
 Escherweg 2             http://eis.informatik.uni-oldenburg.de/~martin



Mon, 02 Oct 2000 03:00:00 GMT  
 
 [ 2 post ] 

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