generate loops 
Author Message
 generate loops

I've been trying to use a "for ... generate" loop to instanciate a
series of components, but my atempts fail will an error which suggests
that the loop does nothing.  Can anyone see anything wrong with the
following code?  big_thing is supposed to be made up from three
instances of slice, each of which is passed a value of enum_type as a
generic.  When I try to analyse this with Synopsys VSS, I get this
message:

    for all: slice use entity work.slice(e);
             ^
Warning: vhdlan,782 gen.vhd(37):
    Component is never instanced in the corresponding set of statements.

Please Help!  Here is the code:

package t_pack is
  type enum_type is ( fred, jim, bill );
end t_pack;

use work.t_pack.all;

entity slice is
  generic ( destination : enum_type );
  port ( x : in bit  );
end slice;

architecture e of slice is
begin
end e;

use work.t_pack.all;

entity big_thing is
end big_thing;

architecture e of big_thing is
  component slice
    generic ( destination : enum_type );
    port ( x : in bit );
  end component;
  signal a : bit;
begin
  gen_loop : for index in fred to bill generate
    routing_slice : slice generic map ( index )
                          port map ( a );
  end generate;
end e;

configuration test_n of big_thing is
  for e
    for all: slice use entity work.slice(e);
    end for;
  end for;
end test_n;

--Phil.



Wed, 07 Aug 1996 06:15:03 GMT  
 generate loops

Quote:

>I've been trying to use a "for ... generate" loop to instanciate a
>series of components, but my atempts fail will an error which suggests
>that the loop does nothing.  Can anyone see anything wrong with the
>following code?  big_thing is supposed to be made up from three
>instances of slice, each of which is passed a value of enum_type as a
>generic.  When I try to analyse this with Synopsys VSS, I get this
>message:

>    for all: slice use entity work.slice(e);
>             ^
>Warning: vhdlan,782 gen.vhd(37):
>    Component is never instanced in the corresponding set of statements.

>Please Help!  Here is the code:

... code deleted ...

Quote:
>configuration test_n of big_thing is
>  for e
>    for all: slice use entity work.slice(e);
>    end for;
>  end for;
>end test_n;

Your configuration is missing the generate block.
Each nested block within an architecture requires a corresponding:
    for block-name
        { component-configuration | block-configuration }
    end for;

That includes generate blocks.
The following configuration does the job.

configuration test_n of big_thing is
  for e
    for gen_loop
        for all: slice use entity work.slice(e);
        end for;
    end for;
  end for;
end test_n;

In the outside block the component slice never was instanced ... only
inside the generate block.  Hence the compiler error.

olaf



Thu, 08 Aug 1996 03:34:36 GMT  
 generate loops

Quote:
>     for all: slice use entity work.slice(e);
>              ^
> Warning: vhdlan,782 gen.vhd(37):
>     Component is never instanced in the corresponding set of statements.

                         ^^^^^^^^^
I wish VHDL tools were literate enough to use correct terminology.
(The verb used by the LRM is instantiated.)

Oh well...ours aren't quite right either some days.

Daniel
--
Daniel S. Barclay                              Suite 101, 5457 Twin Knolls Road
COMPASS Design Automation, Inc.                        Columbia, MD  21045  USA



Fri, 09 Aug 1996 20:42:19 GMT  
 
 [ 3 post ] 

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