Student needs help. 
Author Message
 Student needs help.

I'm a student doing a VHDL basic course as part of a post graduate
qualification and am had some problems which I found hard to solve.

A basic test bench is shown below:

library ieee;
use ieee.std_logic_1164.all;

Entity testbench IS

End testbench;

Architecture Structural of testbench is

        Component Cascade

                PORT(clk,RS,LS,Ms_rst : IN STD_LOGIC;
                shiftdir, enb_out : IN STD_LOGIC_VECTOR(0 TO 1);
                D_bus : INOUT STD_LOGIC_VECTOR(0 TO 15) BUS;
                ORight,OLeft : OUT STD_LOGIC);

        End Component;

        For test:cascade use entity work.design(structural);

        Signal  clk,LS,RS,Ms_rst : STD_logic;
        Signal  shiftdir, enb_out : STD_LOGIC_VECTOR(0 TO 1);
        Signal  D_bus :  STD_LOGIC_VECTOR(0 TO 15) BUS;
        Signal  ORight,OLeft : STD_LOGIC;
begin

--Clock

process

        begin
                if clk='0'
                        then clk<='1';
                else clk<='0';
                end if;
                wait for 50 ns;

end process;    

LS<='1';
RS<='1';
ms_rst <='0', '1' after 40 ns;
io <="1111111111111111";
shiftdir <="11","10" after 200 ns, "01" after 800 ns;
enb_out <="11","00" after 100 ns, "11" after 1400 ns;  

        test:cascade    

        PORT MAP (clk=> clk,ms_rst=>ms_rst, RS=>RS, LS=>LS,
        shiftdir=>shiftdir,enb_out=>enb_out, D_bus=>D_bus, Oleft=>Oleft,
        Oright=>Oright);

end structural;

wen I tried to compile this using Mentor graphics system "qvhcom" command a
compiler error about not being able to resolve guarded signals.  As none of
mys entities or archtitecures use guards I have no idea why this happens.

Any help would be greatly appreciated.

J. Pendrigh



Tue, 26 Jun 2001 03:00:00 GMT  
 Student needs help.

Quote:
> J. Pendrigh
> library ieee;
> use ieee.std_logic_1164.all;

> Entity testbench IS
> End testbench;

> Architecture Structural of testbench is
>         Component Cascade
>                 PORT(clk,RS,LS,Ms_rst : IN STD_LOGIC;
>                 shiftdir, enb_out : IN STD_LOGIC_VECTOR(0 TO 1);
>                 D_bus : INOUT STD_LOGIC_VECTOR(0 TO 15) BUS;
>                 ORight,OLeft : OUT STD_LOGIC);
>         End Component;
>-------> For test:cascade use entity work.design(structural);
>         Signal  clk,LS,RS,Ms_rst : STD_logic;
>         Signal  shiftdir, enb_out : STD_LOGIC_VECTOR(0 TO 1);
>         Signal  D_bus :  STD_LOGIC_VECTOR(0 TO 15) BUS;
>         Signal  ORight,OLeft : STD_LOGIC;
> begin
> --Clock
>.....
>         test:cascade
>         PORT MAP (clk=> clk,ms_rst=>ms_rst, RS=>RS, LS=>LS,
>         shiftdir=>shiftdir,enb_out=>enb_out, D_bus=>D_bus, Oleft=>Oleft,
>         Oright=>Oright);
> end structural;

configuration cascade_veri of testbench
    for Structural  -- Architecture name of testbench
       for test : cascade use entity work.cascade(structural);
                  -- structural : Architecture name of cascade
       end for;
    end for;
end cascade_veri;

Maybe, above method is right, isn't it?
I'm using Synopsys VSS, so I'll
% vhdlan testbentch.vhd  #compile
% vhdlsim cascade_veri   #excute

-- ***************************************
-- Jang, Kyungjin
-- DIT 2R, Daewoo Electronics CO., LTD.


-- <http://203.228.135.73>
-- ***************************************

-- ***************************************
-- Jang, Kyungjin
-- DIT 2R, Daewoo Electronics CO., LTD.


-- <http://203.228.135.73>
-- ***************************************



Wed, 27 Jun 2001 03:00:00 GMT  
 
 [ 2 post ] 

 Relevant Pages 

1. Help...college student needs help w/cobol prgm.

2. How to? (student need help)

3. A student need Help with Smalltalk

4. student needs help

5. Student needs help, please

6. Desperate college students need help!!!

7. Student needs help

8. Student needs HELP!!!

9. Student needs HELP!!!

10. student needs help for his project

11. Struggling student needs help

12. Student need help

 

 
Powered by phpBB® Forum Software