If high is more than 3ea of 16 input , result is 1
Author Message
If high is more than 3ea of 16 input , result is 1

input =  16 bit,

If high is more than 3ea of 16 input
result  = '1'
else
result  = '0'

How can I do vhdl?

Sat, 10 Sep 2005 16:48:43 GMT
If high is more than 3ea of 16 input , result is 1

Quote:

> input =  16 bit,

> If high is more than 3ea of 16 input
> result  = '1'
> else
> result  = '0'

> How can I do vhdl?

A simple counter for the '1' values should do it. Keep it ranged from 0 to
3.

cnt := 0; -- initialise counter
result <= '0'; -- default value for result
FOR i IN 0 TO 15 LOOP
IF input(i) = '1' THEN
IF cnt = 3 THEN -- 3 already counted, and one more this time makes > 3
result <= '1'
cnt := 3;
ELSE
cnt := cnt + 1;
END IF;
END IF;
END LOOP;

Or something like that. :)

Regards,

Pieter Hulshoff

Sun, 11 Sep 2005 02:43:21 GMT
If high is more than 3ea of 16 input , result is 1

Quote:

> > input =  16 bit,

> > If high is more than 3ea of 16 input
> > result  = '1'
> > else
> > result  = '0'

> > How can I do vhdl?

> A simple counter for the '1' values should do it. Keep it ranged from 0 to
> 3.
...
> Pieter Hulshoff

As Pieter Hulshoff noted you could use a sequential circuit to select
each bit and count up to three or more.  I didn't realize that
synthesizers were smart enough to do a for loop (mux and counter).
One problem with this is if the inputs change while you are counting
you could get a false output.  This may be fine as long as you
understand what the circuit does.

You could also use a combinatorial circuit to count the number of bits
and then check to see if it is three or more (greater than 2).  If you
think about it a 1 bit adder (A0 + B0) with "Carry In" can tell if 0
3 bits are a one.  This one bit adder has a two bit output.  A two bit
adder could then be used to add up the outputs of the two 1 bit
outputs.  The Carry In of the two and three bit adders can be used to
check for another bit as well.  You could instantiate these adders in
an architectural design as follows:

As usual I will leave the rest of the problem, figuring out three or
more, as an exercise for the student :)

Sun, 11 Sep 2005 09:34:43 GMT
If high is more than 3ea of 16 input , result is 1

Quote:

>> input =  16 bit,

>> If high is more than 3ea of 16 input
>> result  = '1'
>> else
>> result  = '0'

>> How can I do vhdl?

>A simple counter for the '1' values should do it. Keep it ranged from 0 to
>3.

>cnt := 0; -- initialise counter
>result <= '0'; -- default value for result
>FOR i IN 0 TO 15 LOOP
>  IF input(i) = '1' THEN
>    IF cnt = 3 THEN -- 3 already counted, and one more this time makes > 3
>      result <= '1'
>      cnt := 3;
>    ELSE
>      cnt := cnt + 1;
>    END IF;
>  END IF;
>END LOOP;

>Or something like that. :)

This works, but unrolls to 15 cascaded adders, which could be slow.

This problem is actually a good candidate for one of my pet stupid VHDL
tricks: recursive hardware!

The basic idea is that IF-GENERATE can be used to create special case
hardware.

entity MORETHAN3 is
generic(
WIDTH : integer := 16
);
port(
A: in std_ulogic_vector(WIDTH-1 downto 0);
EQN: out std_ulogic_vector(3 downto 0)
);
end MORETHAN3;

architecture RTL of MORETHAN3 is

constant HALF: integer := WIDTH / 2;
signal EQNH, EQNL: std_ulogic_vector(3 downto 0);

begin
-- EQN(i) for i=0,1,2 means "exactly i bits are set".
-- EQN(3) means "3 or more bits set".

-- First the simple cases:
G1: if (WIDTH = 1) generate
EQN(0) <= not A(0);
EQN(1) <= A(0);
EQN(2) <= '0';
EQN(3) <= '0';
end generate;

G2: if (WIDTH = 2) generate
EQN(0) <= not (A(0) or A(1));
EQN(1) <= A(0) xor A(1);
EQN(2) <= A(0) and A(1);
EQN(3) <= '0';
end generate;

-- Now the complex case: we split the circuit in half,
-- compute the quantities for each half, and combine the result.
-- Caution!  If WIDTH is odd, then the halves are not same size!

G3: if (WIDTH > 2) generate

UH: MORETHAN3
generic map(
WIDTH => HALF
)
port map(
A => A(WIDTH-1 downto WIDTH-HALF),
EQN => EQNH
);

UL: MORETHAN3
generic map(
WIDTH => WIDTH - HALF
)
port map(
A => A(WIDTH-HALF-1 downto 0),
EQN => EQNL
);

EQN(0) <= EQNL(0) and EQNH(0);
EQN(1) <= (EQNL(0) and EQNH(1)) or (EQNL(1) and EQNH(0));
EQN(2) <= (EQNL(0) and EQNH(2)) or (EQNL(1) and EQNH(1)) or
(EQNL(2) and EQNH(0));
EQN(3) <= EQNL(3) or EQNH(3) or (EQNL(1) and EQNH(2)) or
(EQNL(2) and EQNH(1));

end generate;
end RTL;

This is untested and uncompiled.  One of the consequences of being
quasi-employed during the tech meltdown.

For 16 inputs, this will expand to 16->8->4->2 and stop there due
to the explicit case for 2.  Assuming two levels of logic for
each layer, in total there are seven levels of logic.  This is likely
better than an adder chain in an ASIC, but based on what Ray Andraka
the FPGA (assuming that synthesis makes a nice bushy tree).

Sun, 11 Sep 2005 20:50:45 GMT
If high is more than 3ea of 16 input , result is 1

Quote:
> This works, but unrolls to 15 cascaded adders, which could be slow.

I would assume that most compilers these days are capable of reducing a 2
bits adder, no carry, with one input being constant "01" to almost nothing.
Then again, I also thought a simple NxM cross-connect should be doable by
Synopsys, and boy was I wrong. :)

Regards,

Pieter Hulshoff

Sun, 11 Sep 2005 21:52:44 GMT

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