SYNOPSYS, XILINX, VHDL mailing list ? 
Author Message
 SYNOPSYS, XILINX, VHDL mailing list ?

I need to know the mailing list about SYNOPSYS and XILINX(XSI) and VHDL.
Is there mailing list for these.

Tue, 27 Oct 1998 03:00:00 GMT  
 SYNOPSYS, XILINX, VHDL mailing list ?

>I need to know the mailing list about SYNOPSYS and XILINX(XSI) and VHDL.
>Is there mailing list for these.

Kim, I run the grassroots "E-mail Synopsys Users Group (ESNUG)" which is
a group of about 4000 design engineers who share the bugs, their workarounds
and their opinions on Synopsys and EDA related products in a free weekly
e-mail newsletter.  This is not something Synopsys, Inc. controls; it's
something user-driven.  A typical sample of what we've recently talked about:

  * - rules of thumb for synthesizing ROM's.

  * - what (anonymous) users have reported about the new cycle based
      simulators various EDA vendors are working on.

  * - what are the best & worst available PCI parts/models available.

  * - useful Verilog checking tools.

  * - a variety of Synopsys bugs & workarounds.

  * - initial customer impressions of Synopsys Behavi{*filter*}Compiler.

  * - is Power Compiler really useful?

  * - how to port from Synopsys to { Mentor, Cadence, ViewLogic }

  * - doing incremental synthesis on SRAM based FPGA's

In running ESNUG I allow engineers to post their info anonymously (if they
request it) because many times that's the only way we can get the real
story.  To join, all you have to do is send an e-mail to me at

of your e-mail and I'll gladly add you to the distrubution list.

                           - John Cooley
                             Part Time EDA Consumer Advocate
                             Full Time ASIC, FPGA & EDA Design Consultant

 Trapped trying to figure out a Synopsys bug?  Want to hear how 4258 other
 users dealt with it ?  Then join the E-Mail Synopsys Users Group (ESNUG)!

     /o o\  /  it's a FEATURE!"                 (508) 429-4357
    (  >  )
     \ - /     - John Cooley, EDA & ASIC Design Consultant in Synopsys,
     _] [_         Verilog, VHDL and numerous Design Methodologies.

     Holliston Poor Farm, P.O. Box 6222, Holliston, MA  01746-6222
   Legal Disclaimer: "As always, anything said here is only opinion."

Wed, 28 Oct 1998 03:00:00 GMT  
 [ 2 post ] 

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