Help : Connecting INOUT std_logic to INOUT std_logic_vector 
Author Message
 Help : Connecting INOUT std_logic to INOUT std_logic_vector

I instantiated a module in my design which includes a port defined
as          
         CHIP_IO : INOUT std_logic_vector(N downto 0).  

My design includes a port defined as
         BND_IO : INOUT std_logic.  

Is there a way to connect BND_IO to CHIP_IO(0)?  I have been unable to
get anything to compile.

Thanks for any suggestions.

Scott Shaffer



Fri, 19 May 2000 03:00:00 GMT  
 Help : Connecting INOUT std_logic to INOUT std_logic_vector

Quote:

> I instantiated a module in my design which includes a port defined
> as
>          CHIP_IO : INOUT std_logic_vector(N downto 0).

> My design includes a port defined as
>          BND_IO : INOUT std_logic.

> Is there a way to connect BND_IO to CHIP_IO(0)?  I have been unable to
> get anything to compile.

> Thanks for any suggestions.

> Scott Shaffer

You could split the CHIP_IO bus in the port map. For instance, the
following compiles fine:

library IEEE;
use IEEE.std_logic_1164.all;

entity DESIGN is
  port( BND_IO : inout STD_LOGIC );
end DESIGN;

architecture A of DESIGN is
  component MODULE is
    generic( N : POSITIVE );
    port( CHIP_IO : inout STD_LOGIC_VECTOR( N downto 0 ) );
  end component;
  constant WIDTH : POSITIVE := 16;
  signal THE_OTHER_BITS : STD_LOGIC_VECTOR( WIDTH-1 downto 0 );
begin
  INSTANCE: MODULE
              generic map( N => WIDTH )
              port map( CHIP_IO( 0 ) => BND_IO,
                        CHIP_IO( WIDTH downto 1 ) => THE_OTHER_BITS
                      );
end A;

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 Escherweg 2             http://eis.informatik.uni-oldenburg.de/~martin



Sat, 20 May 2000 03:00:00 GMT  
 
 [ 2 post ] 

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