VHDL SRAM models updated 
Author Message
 VHDL SRAM models updated

I just updated our generic VHDL model for simulating typical SRAM
devices. The models are available at

http://www.*-*-*.com/

Some of the features supported by these SRAM models are:

   o  generic memory size, width and timing parameters
   o  18 typical SRAM timing parameters supported
   o  clear-on-power-up and/or download-on-power-up (requested by generic)
   o  RAM dump into or download from an ASCII-file (requested by signal)
   o  pair of active-low and active-high Chip-Enable signals
   o  nWE-only memory access control
   o  many (but not all) timing and access control violations asserted.

Hope you find the models useful. Please give feedback.

--
---------------------------------------------------------------------------
Andre' Klindworth                       Universitaet Hamburg, FB Informatik

http://www.*-*-*.com/



Tue, 02 Feb 1999 03:00:00 GMT  
 
 [ 1 post ] 

 Relevant Pages 

1. VHDL/Verilog models for memory (SRAM and DRAM)

2. SRAM vhdl model wanted

3. VHDL model for SRAM

4. Looking for SRAM VHDL model

5. where can i get vhdl models for a sram and microcontrollers

6. Dual Port Sram Vhdl Model

7. Pipeline Burst SRAM VHDL simulation Model

8. VHDL SRAM model for testbench?

9. SRAM model in VHDL wanted

10. WANTED SRAM VHDL MODEL

11. VHDL model of SRAM wanted

12. VHDL/Verilog models for memory (SRAM and DRAM)

 

 
Powered by phpBB® Forum Software