VHDL SRAM models updated 
Author Message
 VHDL SRAM models updated

I just updated our generic VHDL model for simulating typical SRAM
devices. The models are available at


Some of the features supported by these SRAM models are:

   o  generic memory size, width and timing parameters
   o  18 typical SRAM timing parameters supported
   o  clear-on-power-up and/or download-on-power-up (requested by generic)
   o  RAM dump into or download from an ASCII-file (requested by signal)
   o  pair of active-low and active-high Chip-Enable signals
   o  nWE-only memory access control
   o  many (but not all) timing and access control violations asserted.

Hope you find the models useful. Please give feedback.

Andre' Klindworth                       Universitaet Hamburg, FB Informatik


Tue, 02 Feb 1999 03:00:00 GMT  
 [ 1 post ] 

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