How to use the same VHDL source for different projects 
Author Message
 How to use the same VHDL source for different projects

 Hi,
Im trying to produce two slightly different products with the same VHDL
sources.
In each product there are some features to be add or subtract.
The reasons are obvious:
1. One design group can work on two projects simultaneously.
2. Each project will contain only the needed hardware, saving unnecessary
silicon.

Is there a way to determine what features will be simulated (and
synthesized) by using, let say, a different package?

Any idea about how it should be done is welcome.

Thanks in advance
 Ronen



Sun, 26 Jan 2003 03:00:00 GMT  
 How to use the same VHDL source for different projects
Use a preprocessor e.q. Borland CPP with #ifdef , #else and #endif

Hans



Quote:
> Hi,
> I'm trying to produce two slightly different products with the same VHDL
> sources.
> In each product there are some features to be add or subtract.
> The reasons are obvious:
> 1. One design group can work on two projects simultaneously.
> 2. Each project will contain only the needed hardware, saving unnecessary
> silicon.

> Is there a way to determine what features will be simulated (and
> synthesized) by using, let say, a different package?

> Any idea about how it should be done is welcome.

> Thanks in advance
>  Ronen



Sun, 26 Jan 2003 03:00:00 GMT  
 How to use the same VHDL source for different projects

Quote:

>  Hi,
> I?m trying to produce two slightly different products with the same VHDL
> sources.
> In each product there are some features to be add or subtract.
> The reasons are obvious:
> 1. One design group can work on two projects simultaneously.
> 2. Each project will contain only the needed hardware, saving unnecessary
> silicon.

> Is there a way to determine what features will be simulated (and
> synthesized) by using, let say, a different package?

> Any idea about how it should be done is welcome.

> Thanks in advance
>  Ronen

Generic parameters and generate statements are exactly what you
need.

Regards,
--
Renaud Pacalet, ENST / COMELEC, 46 rue Barrault 75634 Paris Cedex 13



Sun, 26 Jan 2003 03:00:00 GMT  
 How to use the same VHDL source for different projects

Quote:


> >  Hi,
> > I?m trying to produce two slightly different products with the same VHDL
> > sources.
> > In each product there are some features to be add or subtract.
> > The reasons are obvious:
> > 1. One design group can work on two projects simultaneously.
> > 2. Each project will contain only the needed hardware, saving unnecessary
> > silicon.

> > Is there a way to determine what features will be simulated (and
> > synthesized) by using, let say, a different package?

> > Any idea about how it should be done is welcome.

> > Thanks in advance
> >  Ronen

> Generic parameters and generate statements are exactly what you
> need.

Configurations would come in handy too.

-- Joe Dalton



Sun, 26 Jan 2003 03:00:00 GMT  
 How to use the same VHDL source for different projects
Hi

one possible solution is to declare various constants for your different
requirements and to declare another constant (e.g PROJECT) which gets the
value of one of the declared constants. In your VHDL code you can use a
generate statement to describe the required behaviour. Every group can use
their own package and declare the constant as required.

e.g
if PROJECT = A generate
...
end generate
 if PROJECT = B generate
...
end generate

Hope this helps.

Best Regards

Ansgar Bambynek

P.S.: please remove the x's to reply


Quote:
> Hi,
>Im trying to produce two slightly different products with the same VHDL
>sources.
>In each product there are some features to be add or subtract.
>The reasons are obvious:
>1. One design group can work on two projects simultaneously.
>2. Each project will contain only the needed hardware, saving unnecessary
>silicon.

>Is there a way to determine what features will be simulated (and
>synthesized) by using, let say, a different package?

>Any idea about how it should be done is welcome.

>Thanks in advance
> Ronen



Sun, 26 Jan 2003 03:00:00 GMT  
 How to use the same VHDL source for different projects
On Wed, 9 Aug 2000 14:57:09 +0200, Ronen Goldberg


Quote:
> I'm trying to produce two slightly different products with the same VHDL
> sources.
> In each product there are some features to be add or subtract.
> The reasons are obvious:
> 1. One design group can work on two projects simultaneously.
> 2. Each project will contain only the needed hardware, saving unnecessary
> silicon.
> Is there a way to determine what features will be simulated (and
> synthesized) by using, let say, a different package?

If generates whose conditions are controlled by generics or package-
resident constants is one obvious way.

If this method doesn't work or is otherwise inconvenient, a
preprocessor like cpp or a macro expander like m4 might also work.

Paul

--
              |"EDA tools are a cruel joke inflicted on electronics designers
Paul Menchini | by computer scientists, and stating that a software-programming
www.mench.com | language can describe hardware is the continuation of the same
              | {*filter*}ic behavior."     -- Gabe Moretti



Sun, 26 Jan 2003 03:00:00 GMT  
 
 [ 6 post ] 

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