Don't care in VHDL ??? 
Author Message
 Don't care in VHDL ???

I can't successfully compile the simple VHDL code for address decode.
Previously design was done on AHDL and portion of it looked like the
following:

CS_0 = !((A[15..0] == b"0000xxxxxxxx") & !ALE ); % 0000 - 0FFF %
CS_1 = !((A[15..0] == b"0001xxxxxxxx") & !ALE ); % 1000 - 1FFF %;
CS_2 = .......................................................;
----------------------------------------------------------------------------
In VHDL I didn't achieved any results with "don't care" bits and
finally part of the code looks like:

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;

entity ADec is
        port  ( A       : in std_logic_vector (15 downto 0);
                ALE     : in std_logic;
                CS_0    : out std_logic;
                CS_1    : out std_logic;
                CS_2    : out std_logic;
                .....................................
                 );
end entity ADec;

architecture Arch_ADec of ADec is
        begin
        CS_0 <= '0' when(A >=x"0000" and A <=x"0FFF" and ALE = '0')
else '1';               --      0000 - 0FFF
        CS_1 <= '0' when(A >=x"1000" and A <=x"1FFF" and ALE = '0')
else '1';               --      1000 - 1FFF
        CS_2 <= ...................
        .................................
end ArchMLU_ADecoder;

The design works, but I think this is not a best way to do it. It's
not readable and, what is much more important - it's bad for synthesis
if synthesis tools will leave it as is.

Any help will be very appreciated.



Sat, 22 Feb 2003 21:40:25 GMT  
 Don't care in VHDL ???
Leon a crit :

Quote:

> I can't successfully compile the simple VHDL code for address decode.
> Previously design was done on AHDL and portion of it looked like the
> following:

> CS_0 = !((A[15..0] == b"0000xxxxxxxx") & !ALE ); % 0000 - 0FFF %
> CS_1 = !((A[15..0] == b"0001xxxxxxxx") & !ALE ); % 1000 - 1FFF %;
> CS_2 = .......................................................;
> In VHDL I didn't achieved any results with "don't care" bits and
> finally part of the code looks like:

[...]
> architecture Arch_ADec of ADec is
>   begin
>     CS_0 <= '0' when(A >=x"0000" and A <=x"0FFF" and ALE = '0')
>                 else '1';               --      0000 - 0FFF
>         CS_1 <= '0' when(A >=x"1000" and A <=x"1FFF" and ALE = '0')
>                 else '1';               --      1000 - 1FFF
>         CS_2 <= ...................
>         .................................
> end ArchMLU_ADecoder;

> The design works, but I think this is not a best way to do it. It's
> not readable and, what is much more important - it's bad for
> synthesis if synthesis tools will leave it as is.

From what I see, you don't have to compare the lower bits. Why don't you
just write:

CS_0 <= '0' when A(15 DOWNTO 12) = "0000" and ALE = '0' else '1';

And so on...
Just drop what you don't care about.

--
Nicolas MATRINGE           DotCom S.A.
Conception electronique    16 rue du Moulin des Bruyeres
Tel +33 1 46 67 51 11      F-92400 COURBEVOIE - FRANCE
Fax +33 1 46 67 51 01      http://www.dotcom.fr/



Sat, 22 Feb 2003 22:16:08 GMT  
 Don't care in VHDL ???

Quote:

>I can't successfully compile the simple VHDL code for address decode.
>Previously design was done on AHDL and portion of it looked like the
>following:

>CS_0 = !((A[15..0] == b"0000xxxxxxxx") & !ALE ); % 0000 - 0FFF %
>CS_1 = !((A[15..0] == b"0001xxxxxxxx") & !ALE ); % 1000 - 1FFF %;
>CS_2 = .......................................................;
>---------------------------------------------------------------------------
-
>In VHDL I didn't achieved any results with "don't care" bits and
>finally part of the code looks like:

>library IEEE;
>use IEEE.std_logic_1164.all;
>use IEEE.std_logic_arith.all;
>use IEEE.std_logic_unsigned.all;

>entity ADec is
> port  ( A : in std_logic_vector (15 downto 0);
> ALE : in std_logic;
> CS_0 : out std_logic;
> CS_1 : out std_logic;
> CS_2 : out std_logic;
> .....................................
>          );
>end entity ADec;

>architecture Arch_ADec of ADec is
> begin
> CS_0 <= '0' when(A >=x"0000" and A <=x"0FFF" and ALE = '0')
>else '1'; -- 0000 - 0FFF
> CS_1 <= '0' when(A >=x"1000" and A <=x"1FFF" and ALE = '0')
>else '1'; -- 1000 - 1FFF
> CS_2 <= ...................
> .................................
>end ArchMLU_ADecoder;

>The design works, but I think this is not a best way to do it. It's
>not readable and, what is much more important - it's bad for synthesis
>if synthesis tools will leave it as is.

>Any help will be very appreciated.

Hi Leon,

Use the std_match() function when comparing signals to constants containing
don't cares.

CS_0 <= '0' when ALE = '0' and std_match(A, "0000XXXXXXXXXXXX") else '1';

Karl



Sat, 22 Feb 2003 22:28:37 GMT  
 Don't care in VHDL ???
On Tue, 05 Sep 2000 14:28:37 GMT, "Karl Olsen"

THanks a lot,

One question - where does this function live?

Quote:

>Hi Leon,

>Use the std_match() function when comparing signals to constants containing
>don't cares.

>CS_0 <= '0' when ALE = '0' and std_match(A, "0000XXXXXXXXXXXX") else '1';

>Karl



Sun, 23 Feb 2003 00:19:16 GMT  
 Don't care in VHDL ???
Hi,


Quote:
> One question - where does this function live?


In IEEE.NUMERIC_STD

Srini



Sun, 23 Feb 2003 00:34:24 GMT  
 Don't care in VHDL ???
Is there a list of the functions contained in numeric_std, and other libraries
somewhere?  This is one of those nice to have functions I wasn't aware was in
there.  I think the hardest part of coming up to speed on VHDL is the lack of
documentation as to what the functions are and where they reside.  The
textbooks, and even on-line help all seem to focus only on std_logic, not on the
more standard numeric_std.

Quote:

> Hi,



> > One question - where does this function live?

> In IEEE.NUMERIC_STD

> Srini

--
-Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950

http://www.andraka.com  or http://www.fpga-guru.com


Sun, 23 Feb 2003 02:37:49 GMT  
 Don't care in VHDL ???
Hi Lon,

You must use the dash symbol ('-') instead of "x".

Denis.



Quote:
> I can't successfully compile the simple VHDL code for address decode.
> Previously design was done on AHDL and portion of it looked like the
> following:

> CS_0 = !((A[15..0] == b"0000xxxxxxxx") & !ALE ); % 0000 - 0FFF %
> CS_1 = !((A[15..0] == b"0001xxxxxxxx") & !ALE ); % 1000 - 1FFF %;
> CS_2 = .......................................................;
> --------------------------------------------------------------------------
--
> In VHDL I didn't achieved any results with "don't care" bits and
> finally part of the code looks like:

> library IEEE;
> use IEEE.std_logic_1164.all;
> use IEEE.std_logic_arith.all;
> use IEEE.std_logic_unsigned.all;

> entity ADec is
> port  ( A : in std_logic_vector (15 downto 0);
> ALE : in std_logic;
> CS_0 : out std_logic;
> CS_1 : out std_logic;
> CS_2 : out std_logic;
> .....................................
>          );
> end entity ADec;

> architecture Arch_ADec of ADec is
> begin
> CS_0 <= '0' when(A >=x"0000" and A <=x"0FFF" and ALE = '0')
> else '1'; -- 0000 - 0FFF
> CS_1 <= '0' when(A >=x"1000" and A <=x"1FFF" and ALE = '0')
> else '1'; -- 1000 - 1FFF
> CS_2 <= ...................
> .................................
> end ArchMLU_ADecoder;

> The design works, but I think this is not a best way to do it. It's
> not readable and, what is much more important - it's bad for synthesis
> if synthesis tools will leave it as is.

> Any help will be very appreciated.



Sun, 23 Feb 2003 07:46:37 GMT  
 Don't care in VHDL ???

Quote:

>I can't successfully compile the simple VHDL code for address decode.
>Previously design was done on AHDL and portion of it looked like the
>following:

>CS_0 = !((A[15..0] == b"0000xxxxxxxx") & !ALE ); % 0000 - 0FFF %
>CS_1 = !((A[15..0] == b"0001xxxxxxxx") & !ALE ); % 1000 - 1FFF %;

For the std_logic type, 'x' is a forcing unknown. The 'don't care'
value is '-'. However, a comparison against a '-' will return false
anyway, unless you're comparing against another '-', so it won't help
you in this case.

I wouldn't use 'std_match' as recommended by others; Nicolas's answer
is simpler and faster. Also, in general, your pre- and post-synthesis
simulations may not match if you use std_match, since the simulator
and synthesiser may handle the don't care conditions differently.

I also noticed that you use both std_logic_arith and
std_logic_unsigned in your code. This isn't generally a good idea, and
you should think about why you're using both. You should be able to
use just one or the other or, even better, replace them with the
standard package numeric_std.

Evan



Sun, 23 Feb 2003 16:55:13 GMT  
 Don't care in VHDL ???

Quote:

>Is there a list of the functions contained in numeric_std, and other libraries
>somewhere?  

The only one I know of is the crib sheet on Qualis's web site. I don't
have an address, but try www.qualis.com and look for the 'library' or
something similar. There's also lots of other good stuff.

Evan



Sun, 23 Feb 2003 16:55:32 GMT  
 Don't care in VHDL ???

Quote:

> Hi,



> > Is there a list of the functions contained in numeric_std, and other
> libraries
> > somewhere?  This is one of those nice to have functions I wasn't aware was
> in
> > there.  I think the hardest part of coming up to speed on VHDL is the lack
> of
> > documentation as to what the functions are and where they reside.  The
> > textbooks, and even on-line help all seem to focus only on std_logic, not
> on the
> > more standard numeric_std.

> I agree with you completely :-) Also in the past there used to be a draft
> version available from http://www.vhdl.org/dasc page, but now it has been
> removed I guess (I get a  message saying You Are Not Authorized to see this
> page" bla bla bla..). So a local solution could be to make a list for
> ourselves in our work environment (grep it from numeric_std packege with
> some comments..). A more elegant solution WW could be that

> 1.> Either vhdl.org publishes such a list (and provide an easily reachable
> link - this page is in such a complex shape that every time I visit I end up
> spending hours together looking for what I want)

> 2.> The FAQ adds this (Hi Edwin ! - TIA), but I am not sure if there is a
> copyright issue in this.

> Wish things improve soon :-)

If anyone has such a list, I would be happy to publish it on my web
page. It could be at www.arius.com/vhdlinfo. We could organize
information there in any form that is most readable.

--

Rick Collins


Ignore the reply address. To email me use the above address with the XY
removed.

Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design

Arius
4 King Ave
Frederick, MD 21701-3110
301-682-7772 Voice
301-682-7666 FAX

Internet URL http://www.arius.com



Mon, 24 Feb 2003 22:06:16 GMT  
 Don't care in VHDL ???
Hi

Quote:
> If anyone has such a list, I would be happy to publish it on my web
> page. It could be at www.arius.com/vhdlinfo. We could organize
> information there in any form that is most readable.

I wrote a illustrative map which explaining those relations between
std_logic faimilies some years ago, for my customers reference.
 If your web brouser could read japanese charactor set, please refer
a simple page here under
  http://www.saitama-j.or.jp/~sysworks/dsnnote2/VHDL_Package_2.html
  There is a *gif-figure* in the page which explaining what is
appended in that each packages noting what conv-function names and
params to be used.
 If you like my approach, I think I can explain numeric std in
similar manner.
 Though I think it is not really neccesary for experienced guys such
like in this discussion group, it could be a some help for new commer
in VHDL mad-pool.

Sent via Deja.com http://www.deja.com/
Before you buy.



Tue, 25 Feb 2003 09:33:26 GMT  
 Don't care in VHDL ???
Hi

Quote:
> If anyone has such a list, I would be happy to publish it on my web
> page. It could be at www.arius.com/vhdlinfo. We could organize
> information there in any form that is most readable.

I wrote a illustrative map which explaining those relations between
std_logic faimilies some years ago, for my customers reference.
 If your web brouser could read japanese charactor set, please refer
a simple page here under
  http://www.saitama-j.or.jp/~sysworks/dsnnote2/VHDL_Package_2.html
  There is a *gif-figure* in the page which explaining what is
appended in that each packages noting what conv-function names and
params to be used.
 If you like my approach, I think I can explain numeric std in
similar manner.
 Though I think it is not really neccesary for experienced guys such
like in this discussion group, it could be a some help for new commer
in VHDL mad-pool.

Sent via Deja.com http://www.deja.com/
Before you buy.



Tue, 25 Feb 2003 09:33:57 GMT  
 Don't care in VHDL ???

Quote:

> Is there a list of the functions contained in numeric_std, and other libraries
> somewhere?  This is one of those nice to have functions I wasn't aware was in
> there.  I think the hardest part of coming up to speed on VHDL is the lack of
> documentation as to what the functions are and where they reside.  The
> textbooks, and even on-line help all seem to focus only on std_logic, not on the
> more standard numeric_std.


> > Hi,



> > > One question - where does this function live?

> > In IEEE.NUMERIC_STD

> > Srini

> --
> -Ray Andraka, P.E.
> President, the Andraka Consulting Group, Inc.
> 401/884-7930     Fax 401/884-7950

> http://www.andraka.com  or http://www.fpga-guru.com

Hello Ray:

The NUMERIC packages are described in IEEE standard 1076.3 that you can purchase
from the IEEE.

The NUMERIC packages are also described in my book "A VHDL Synthesis Primer, Second
Edition",
ISBN 0-9650391-9-6 (you can get it from amazon.com). All examples in this book are
based on this
standard.

I have also given a number of tutorials since 1996 on the packages at various
conferences: VIUF, ASIC,
HDL, etc.

I was the ballot chair and a major contributor to the development of these packages
...




Wed, 26 Feb 2003 03:52:09 GMT  
 Don't care in VHDL ???
Hi,

Quote:

> Hi,



> > Is there a list of the functions contained in numeric_std, and other
> libraries
> > somewhere?  This is one of those nice to have functions I wasn't aware was
> in
> > there.  I think the hardest part of coming up to speed on VHDL is the lack
> of
> > documentation as to what the functions are and where they reside.  The
> > textbooks, and even on-line help all seem to focus only on std_logic, not
> on the
> > more standard numeric_std.

> I agree with you completely :-) Also in the past there used to be a draft
> version available from http://www.vhdl.org/dasc page, but now it has been
> removed I guess (I get a  message saying You Are Not Authorized to see this
> page" bla bla bla..). So a local solution could be to make a list for
> ourselves in our work environment (grep it from numeric_std packege with
> some comments..). A more elegant solution WW could be that

> 1.> Either vhdl.org publishes such a list (and provide an easily reachable
> link - this page is in such a complex shape that every time I visit I end up
> spending hours together looking for what I want)

> 2.> The FAQ adds this (Hi Edwin ! - TIA), but I am not sure if there is a
> copyright issue in this.

Ok! I appended an incomplete (!) sample set of tables which list some
of the functions  included in ieee.std_logic_1164 and ieee.numeric_std.
Is the table format/style ok? Any comments, suggestions, ... are
welcome!

--
Edwin

=============================================================

The following tables lists operators and functions available in packages
ieee.std_logic_1164 and ieee.numeric_std. The tables list

   * function or operator name
   * first parameter type
   * optional the type of a second parameter
   * return type
   * the package the function/operator resides in
   * some additional remarks

In order to save space type names in the table are abbreviated as follows

     type name       abbreviation                remarks

 integer             int
 natural             nat           all integer >= 0; subtype of integer
 bit                 bit
 bit_vector          bvec
 std_ulogic          sul
 std_ulogic_vector   sulv
 std_logic           s1164         resolved std_ulogic subtype
 std_logic_vector    slv
 unsigned            usd
 signed              sd

Further, package ieee.std_logic_1164 is abbreviated "s1164" and package
ieee.numeric_std is abbreviated "num".

   * Logical operators on std_logic (=sl) / std_ulogic (=sul)

      operator   1st par  2nd par  return package  remarks

      and        sul      sul      sul    s1164
      nand       sul      sul      sul    s1164
      or         sul      sul      sul    s1164
      nor        sul      sul      sul    s1164
      xor        sul      sul      sul    s1164
      xnor       sul      sul      sul    s1164
      not        sul               sul    s1164

   * Logical operators on std_logic_vector (=slv), std_ulogic_vector
     (=sulv), signed (=sd) and unsigned (=usd):

      operator   1st par  2nd par  return package  remarks

      and        sulv     sulv     sulv   s1164    bitwise and
      and        slv      slv      slv    s1164    bitwise and
      and        sd       sd       sd     num      bitwise and
      and        usd      usd      usd    num      bitwise and
      nand       sulv     sulv     sulv   s1164    bitwise nand
      nand       slv      slv      slv    s1164    bitwise nand
      nand       sd       sd       sd     num      bitwise nand
      nand       usd      usd      usd    num      bitwise nand
      or         sulv     sulv     sulv   s1164    bitwise or
      or         slv      slv      slv    s1164    bitwise or
      or         sd       sd       sd     num      bitwise or
      or         usd      usd      usd    num      bitwise or
      nor        sulv     sulv     sulv   s1164    bitwise nor
      nor        slv      slv      slv    s1164    bitwise nor
      nor        sd       sd       sd     num      bitwise nor
      nor        usd      usd      usd    num      bitwise nor
      xor        sulv     sulv     sulv   s1164    bitwise xor
      xor        slv      slv      slv    s1164    bitwise xor
      xor        sd       sd       sd     num      bitwise xor
      xor        usd      usd      usd    num      bitwise xor
      xnor       sulv     sulv     sulv   s1164    bitwise xnor
      xnor       slv      slv      slv    s1164    bitwise xnor
      xnor       sd       sd       sd     num      bitwise xnor
      xnor       usd      usd      usd    num      bitwise xnor
      not        sulv              sulv   s1164    bitwise not
      not        slv               slv    s1164    bitwise not
      not        sd                sd     num      bitwise not
      not        usd               usd    num      bitwise not

   * Conversion functions for std_logic (=sul), X01 (subtype of std_ulogic;
     contains only 'X', '0' and '1'), X01Z (subtype of std_ulogic; contains
     only 'X', '0', '1' and 'Z'), UX01 (subtype of std_ulogic; contains only
     'U', 'X', '0' and '1') and bit (=bit):

      function   1st    2nd    return pack.  remarks
                 par    par

      To_bit     sul    bit    bit    s1164  convert sul to bit; 2nd
                                             parameter defines output for
                                             'U', 'X', 'Z' or '-'
      To_X01     bit           X01    s1164  convert bit to X01; returns
                                             only '0' or '1'
      To_X01     sul           X01    s1164  convert sul to X01
      To_X01Z    bit           X01Z   s1164  convert bit to X01Z; returns
                                             only '0' or '1'
      To_X01Z    sul           X01Z   s1164  convert sul to X01Z
      To_UX01    bit           UX01   s1164  convert bit to UX01; returns
                                             only '0' or '1'
      To_UX01    sul           UX01   s1164  convert sul to UX01

   * Conversion functions for bit_vector (=bvec), std_ulogic_vector (=sulv),
     std_logic_vector (=slv), signed (=sd), unsigned (=usd), integer (=int)
     and natural (=nat):

      function           1st   2nd   return  pack.  remarks
                         par   par

      To_Integer         usd         nat     num    convert usd to natural
      To_Integer         sd          int     num    convert sd to integer
      To_Unsigned        nat   nat   usd     num    convert natural (1st
                                                    par) to usd; 2nd par
                                                    defines bit width of
                                                    result
      To_Unsigned        bvec        usd     num    convert bvec to usd;
                                                    result has same index
                                                    range as parameter
      To_Signed          int   int   sd      num    convert integer (1st
                                                    par) to sd; 2nd par
                                                    defines bit width of
                                                    result
      To_Signed          bvec        sd      num    convert bvec to sd;
                                                    result has same index
                                                    range as parameter
      To_Stdlogicvector  usd         slv     num    convert usd to slv;
                                                    result has same index
                                                    range as parameter
      To_Stdlogicvector  sd          slv     num    convert sd to slv;
                                                    result has same index
                                                    range as parameter
      To_X01             bvec        bvec    s1164  convert bvec to bvec;
                                                    resulting vector
                                                    elements are only of
                                                    'X', '0' or '1'
      To_X01             sulv        sulv    s1164  convert sulv to sulv;
                                                    resulting vector
                                                    elements are only of
                                                    'X', '0' or '1'
      To_X01             slv         slv     s1164  convert slv to slv;
                                                    resulting vector
                                                    elements are only of
                                                    'X', '0' or '1'
      To_X01Z            bvec        bvec    s1164  convert bvec to bvec;
                                                    resulting vector
                                                    elements are only of
                                                    'X', '0', '1' or 'Z'
      To_X01Z            sulv        sulv    s1164  convert sulv to sulv;
                                                    resulting vector
                                                    elements are only of
                                                    'X', '0', '1' or 'Z'
      To_X01Z            slv         slv     s1164  convert slv to slv;
                                                    resulting vector
                                                    elements are only of
                                                    'X', '0', '1' or 'Z'
      To_UX01            bvec        bvec    s1164  convert bvec to bvec;
                                                    resulting vector
                                                    elements are only of
                                                    'U', 'X', '0' or '1'
      To_UX01            sulv
...

read more »



Fri, 28 Feb 2003 18:53:30 GMT  
 
 [ 14 post ] 

 Relevant Pages 

1. don't care in vhdl..

2. don't care the dryers strongly, mould them partly

3. don't care the dryers strongly, mould them partly

4. don't care the dryers strongly, mould them partly

5. Testing for unknowns or don't cares

6. Don't care states in decoders

7. Don't Care in a with...select?

8. Don't cares in expressions

9. How to deal with Don't cares

10. UnInit, Weak Unknown, Don't Care Signals

11. Don't cares in std_logic_vector

12. Don't care for integer?

 

 
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