VHDL syntax a(10 downto 0)<=b(0 to 10)
Author Message
VHDL syntax a(10 downto 0)<=b(0 to 10)

Hi friends,
Very easy VHDL syntax question.
I have
a is std_logic_vector (10 downo 0)
b is std_logic_vector (10 downo 0)
Now I whant that
a(10)<=b(0)
a(1)<=b(1)
....
a(0) <=b(10)

But if I write
a(10 downto 0)<=b(0 to 10)
My compiler gives out a error
How can I do this syntactically correct

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Sun, 19 May 2002 03:00:00 GMT
VHDL syntax a(10 downto 0)<=b(0 to 10)
Hi,

Quote:

> Hi friends,
> Very easy VHDL syntax question.
> I have
> a is std_logic_vector (10 downo 0)
> b is std_logic_vector (10 downo 0)
> Now I whant that
> a(10)<=b(0)
> a(1)<=b(1)
> ....
> a(0) <=b(10)

> But if I write
> a(10 downto 0)<=b(0 to 10)
> My compiler gives out a error
> How can I do this syntactically correct

The range of a slice must match the range definition of the array.
Hence, it is not allowed to write "b(0 to 10)" as "b" is defined
in descending order. A slice gives you just a part of an array
without reordering it!

You may write something like

a <= b(0) & b(1) & b(2) & .... & b(10);

So you have still a lot to type but at least only a single
line is required. Of course you may also write a function
to do the job.

--
Edwin

Sun, 19 May 2002 03:00:00 GMT
VHDL syntax a(10 downto 0)<=b(0 to 10)
Hi Bonio,

Try this inside a process:

for I in a'range loop
a(I)<=b(b'low+a'high-I);
end loop;

or outside:

L1:for I in a'range generate
L2:a(I)<=b(b'low+a'high-I);
end generate;

Catalin

Quote:

> Hi friends,
> Very easy VHDL syntax question.
> I have
> a is std_logic_vector (10 downo 0)
> b is std_logic_vector (10 downo 0)
> Now I whant that
> a(10)<=b(0)
> a(1)<=b(1)
> ....
> a(0) <=b(10)

> But if I write
> a(10 downto 0)<=b(0 to 10)
> My compiler gives out a error
> How can I do this syntactically correct

Sun, 19 May 2002 03:00:00 GMT
VHDL syntax a(10 downto 0)<=b(0 to 10)

I thougth it is any way to make such assignments direkt.
Thank you Catalin and Edwin for you answers,

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Sun, 19 May 2002 03:00:00 GMT
VHDL syntax a(10 downto 0)<=b(0 to 10)
Quote:

> I thougth it is any way to make such assignments direkt.

You can define a function Freverse, put it into a package where you have
other frequently used stuff.
In synthesis such a function is translated into wires, no gates.
FUNCTION Freverse(a:std_logic_vector) RETURN std_logic_vector IS
VARIABLE t:std_logic_vector(a'RANGE);
BEGIN
FOR i IN t'RANGE LOOP
t(i):=a(a'HIGH+a'LOW-i);
END LOOP;
RETURN t;
END Freverse;
Andreas

-----------------------------------------------------------------
Andreas C. Doering
Medizinische Universitaet zu Luebeck
Institut fuer Technische Informatik

Home: http://www.iti.mu-luebeck.de/~doering
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"The fear of the LORD is the beginning of ... science" (Proverbs 1.7)
----------------------------------------------------------------

Fri, 24 May 2002 03:00:00 GMT

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