component configurations 
Author Message
 component configurations

I didn't get any response to a previous posting around this subject so let me
ask a related (hopefully!) simpler question.

The following VHDL:

entity or2 is
  port  (x,y : in Bit := '0';   z: out resolved_bit := '1');
end ;

architecture BEHAVIOUR of or2 Is ...

use work.or2;
use work.res_bit.all; -- contains a bit resolution function
architecture driver of or2_driver Is
 component i_or2
  port
  (i1,i2 : in Bit := '0';
   O: out resolved_bit := '1');
 end component;

 signal i , j : bit;
 signal   res : resolved_bit;
 for tester2:i_or2 use entity or2(BEHAVIOUR)
    port map (x=>i1,y=>i2,z=>o);
 for others:i_or2 use entity or2(BEHAVIOUR)
    port map (x=>i,z=>res,y=>j);
...
contains two configurations, the first associates the respective ports
of the instantiated component with those specified in the component template.
The second supplies a connectivity to be used when this component is
instantiated. These appear to rather different concepts. Presumably in the
second case there needs to be further configuration of the architecture so
that ports with differing names can be associated.

Part of this question relates to understanding configurations but we are also
having problems with differing VHDL analysersthrowing out various instances
of configurations and I'm trying to work out which is correct.

Robert
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Sun, 07 Nov 1993 22:52:20 GMT  
 
 [ 1 post ] 

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