Undetermined Output in 'X' state
Quote:
> If an undetermined state 'X' at the output, mux_o of a logical expression
> included in the process statement such as the
> following:
> process(in0_i,in1_i,sel_i,mux_o)
> begin
> mux_o = (in0_i and not(s)) or (in1_i and s);
> end process;
> What can be done so that the output, mux_o appears as a normal output
signal
> as viewed in the chronogramme of
> the compiler.
> Note: using std_logic type for the signals
> Thank You
You will obtain a X value when you assign a signal in two different
concurrent statements. Have assigned mux_o in other concurrent assignment or
process?
I also see that you read a signal (signal s) in the process, and this signal
is not in the sensitivity list of your process. Is signal s sel_i? If not,
you should check the sensitivity list. If you are interested I know a tool
to perform code and hardware-oriented checkers in the VHDL code of the
design.
Fernando Casado