ISE 4.2 and Modelsim (part 2) 
Author Message
 ISE 4.2 and Modelsim (part 2)

Hello!

    First of all I would like to thank Andre for his help!

    I am unsing Xilinx's ISE 4.2i for writing VHDL and then I create a
testbench to open Modelsim for simulation. When I try "Behavioural VHDL
model" everything works fine! But when I try "Post translate VHDL model",
"Post-Map VHDL model" or Post-Place & Route VHDL model" simulation, the
relsulting waveforms seem ok, but Modelsim creates many Warnings (in various
times) such as the one bellow (note: I do not have a clk in this design,
because it is combinational):

** Warning: */X_SUH SETUP  Low VIOLATION ON I WITH RESPECT TO CLK;
#   Expected := 4.084 ns; Observed := 0 ns; At : 0 ns
#    Time: 0 ps  Iteration: 1  Instance: /testbench/uut/gsuh_data_4_rden_1

Does anyone knows what it means?

Also, I would like to ask something else: what is the difference in the
following codes:

code1:
------
if A='1' then
    b<=c;
end if;

code2:
-------
if A='1' then
    b<=c;
else
   b<=b;
end if;

If I use code2, am I going to have troubles in implementation? Is there
going to be a difference in hardware that will be used?

 Thank you very much, in advance, for your time!

Dimitris



Sat, 17 Sep 2005 22:02:00 GMT  
 
 [ 1 post ] 

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