
Synthesizable fixed and/or floating point multiplier and divider
I am looking for synthesizable fixed and floating point multipliers and
dividers. I need to evaluate how well each will fit in an FPGA for
project I am working on. I am using Synopsys so VHDL that is intended for
synthesis by Synopsys is prefered, but anything would be a start.
I am new to this group so I hope that this request is appropriate.
Thanks.
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Cameron McNairy