( rising_edge ( CLK ) ) 
Author Message
 ( rising_edge ( CLK ) )

I've been looking at a fair amount of code published here which refers
to " if (clk'event and clk='1')" as opposed to the method I use which is
"if ( rising_edge ( CLK ) )" of "if ( falling_edge ( CLK ) )". As far as
I'm aware these two functions operate in the same way. Do they, or am I
missing something ??

                                Pat Dobson.



Sun, 27 Jan 2002 03:00:00 GMT  
 ( rising_edge ( CLK ) )

Quote:

> I've been looking at a fair amount of code published here which refers
> to " if (clk'event and clk='1')" as opposed to the method I use which is
> "if ( rising_edge ( CLK ) )" of "if ( falling_edge ( CLK ) )". As far as
> I'm aware these two functions operate in the same way. Do they, or am I
> missing something ??

Nope, they're the same thing.  The "rising_edge()" version is more modern, and
was implemented in the IEEE 1164-1993 VHDL standard (vs. '1987').  Personally, I
use the rising_edge() version because it's a little more readable.

--
Wade D. Peterson
Silicore Corporation
3525 E. 27th St. No. 301, Minneapolis, MN USA 55406
TEL: (612) 722-3815, FAX: (612) 722-5841



Sun, 27 Jan 2002 03:00:00 GMT  
 ( rising_edge ( CLK ) )
Hi,

Quote:

> I've been looking at a fair amount of code published here which refers
> to " if (clk'event and clk='1')" as opposed to the method I use which is
> "if ( rising_edge ( CLK ) )" of "if ( falling_edge ( CLK ) )". As far as
> I'm aware these two functions operate in the same way. Do they, or am I
> missing something ??

It depends on the type of "clk":  if it is of type bit then
"if (clk'event and clk='1')" will work as intended. However, if its type is
"std_logic" then all transitions ending on '1'  (e.g. 'H' (weak 1) --> '1' )
are treated as rising edges!

The function "rising_edge" is defined as follows:

FUNCTION rising_edge  (SIGNAL s : std_ulogic) RETURN BOOLEAN IS
    BEGIN
        RETURN (s'EVENT AND (To_X01(s) = '1') AND
                            (To_X01(s'LAST_VALUE) = '0'));
    END;

"To_X01" converts all std_logic values to an appropriate value  '0', '1' or 'X'.
Hence, "rising_edge" will trigger on 'L' (weak 0) --> '1' but not on
'H' (weak 1) --> '1' .

--
Edwin



Sun, 27 Jan 2002 03:00:00 GMT  
 ( rising_edge ( CLK ) )
On Wed, 11 Aug 1999 08:49:57 -0500, Wade D. Peterson


Quote:


>> I've been looking at a fair amount of code published here which refers
>> to " if (clk'event and clk='1')" as opposed to the method I use which is
>> "if ( rising_edge ( CLK ) )" of "if ( falling_edge ( CLK ) )". As far as
>> I'm aware these two functions operate in the same way. Do they, or am I
>> missing something ??

> Nope, they're the same thing.  The "rising_edge()" version is more
> modern, and was implemented in the IEEE 1164-1993 VHDL standard
> (vs. '1987').  Personally, I use the rising_edge() version because
> it's a little more readable.

In the context of package IEEE.std_logic_1164 (where the only standard
definition of rising_edge occurs) and simulation, they are most
definitely not the same.

"clock'event and clock = '1'" returns true on any transition to '1',
which not only includes '0'->'1' and 'L'->'1', but 'H'->'1', 'U'->'1',
etc.  Moreover, it returns false on '0'->'H'.  So, it's not a reliable
edge detector for std_(u)logic clocks, although it works fine for
clocks of type bit (where there are only two values).

Use rising_edge, if your tools support it.  Unfortunately, not all
synthesis tools do, but it's getting better....

BTW, "rising_edge" and "falling_edge" are implemented in IEEE Std
1164-1993 ("std_logic_1164").  The "-1993" means the year the standard
was approved by the IEEE, and not the version of VHDL to which it
applies.  There is no IEEE Std 1164-1987.

Paul

--

Cadence Design Systems | www.orcad.com   | spread fear, uncertainty and
P.O. Box 71767         | 919-479-1670[v] | doubt in the users' minds."
Durham, NC  27722-1767 | 919-479-1671[f] |  --Don Jones, MS's Y2K Product Mgr



Sun, 27 Jan 2002 03:00:00 GMT  
 ( rising_edge ( CLK ) )
I agree that the previous comments about rising_edge() are true for
simulation. However, for synthesis, I'll bet both generate an edge
triggered flip flop. Where I'm at, we use (clk'event and clk = '1'). Of
course we've been at it for some time and tend not to use the VHDL 93
extensions out of habit.

Interesting...

PJ



Quote:

> I've been looking at a fair amount of code published here which refers
> to " if (clk'event and clk='1')" as opposed to the method I use which
is
> "if ( rising_edge ( CLK ) )" of "if ( falling_edge ( CLK ) )". As far
as
> I'm aware these two functions operate in the same way. Do they, or am
I
> missing something ??

>                                 Pat Dobson.

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Share what you know. Learn what you don't.


Sun, 27 Jan 2002 03:00:00 GMT  
 ( rising_edge ( CLK ) )


Quote:
> I agree that the previous comments about rising_edge() are true for
> simulation. However, for synthesis, I'll bet both generate an edge
> triggered flip flop. Where I'm at, we use (clk'event and clk =
> '1'). Of course we've been at it for some time and tend not to use
> the VHDL 93 extensions out of habit.

There seems to be a common misperception that rising_edge is a
VHDL'93-only feature.  It is not.  It is a function defined as
part of the std_logic_1164 package and works with either version
of VHDL.

Paul

--

Cadence Design Systems | www.orcad.com   | spread fear, uncertainty and
P.O. Box 71767         | 919-479-1670[v] | doubt in the users' minds."
Durham, NC  27722-1767 | 919-479-1671[f] |  --Don Jones, MS's Y2K Product Mgr



Sun, 27 Jan 2002 03:00:00 GMT  
 ( rising_edge ( CLK ) )

    Hi Pat,

in my opinion there's a very prozaic reason for it :

The {*filter*} syntesis tool did some kind of pattern recognition for FF
inferring.

The pattern was if (clk'event and clk='1') and alikes.
The if (rising_edge(clk)) was not recognized , although it's indeed much
cleaner.

Nowadays it is also supported by that synthesis tool.

Apart from that , mind Edwin Naroska's remarks about H and L states.
But I don't think that for a clock those are of great concern ...

Best regards,

Jos

Quote:

> I've been looking at a fair amount of code published here which refers
> to " if (clk'event and clk='1')" as opposed to the method I use which is
> "if ( rising_edge ( CLK ) )" of "if ( falling_edge ( CLK ) )". As far as
> I'm aware these two functions operate in the same way. Do they, or am I
> missing something ??

>                                 Pat Dobson.



Mon, 28 Jan 2002 03:00:00 GMT  
 ( rising_edge ( CLK ) )
Even though the tools that I use support rising_edge() and
falling_edge() functions, I still prefer to use 'event signal attribute
for two reasons:

1.) It ensures that the (synthesizable) code is truly tool independent
(there are still a handful of tools that don't support the
aforementioned functions)

2.) It provides a clean method for paramaterizing the active clock edge
used in reusable designs/modules.

Example:
        if (clk'event and clk = ACTIVE_EDGE) then
          ....

Where: ACTIVE_EDGE is declared as a generic parameter of type std_logic.

Quote:

> I've been looking at a fair amount of code published here which refers
> to " if (clk'event and clk='1')" as opposed to the method I use which is
> "if ( rising_edge ( CLK ) )" of "if ( falling_edge ( CLK ) )". As far as
> I'm aware these two functions operate in the same way. Do they, or am I
> missing something ??

>                                 Pat Dobson.



Wed, 30 Jan 2002 03:00:00 GMT  
 ( rising_edge ( CLK ) )

Quote:

> I've been looking at a fair amount of code published here which refers
> to " if (clk'event and clk='1')" as opposed to the method I use which is
> "if ( rising_edge ( CLK ) )" of "if ( falling_edge ( CLK ) )". As far as
> I'm aware these two functions operate in the same way. Do they, or am I
> missing something ??

>                                 Pat Dobson.

It may also be worth noting that some formal equivalence checkers will not
see these as the same.  This can cause some trouble during QA.

--
Nathan Hackett
Sr. Design Automation Engineer
Silicon Systems inc.



Sun, 03 Feb 2002 03:00:00 GMT  
 
 [ 9 post ] 

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