Synthesizer Bug? ViewLogic, VHDL, and XC4000 
Author Message
 Synthesizer Bug? ViewLogic, VHDL, and XC4000

Hello,

I'm using ViewLogic's WorkView PLUS 5.2 on a pentium.  Using VHDL for an
XC400x digital modem design.  I'm new to their tools, but have found the VHDL
and simulation methodology to be a FANTASTIC time advantage for me.  
Anyway,I find that my VHDL models simulate very predictable behaviorally.  I
use (at least I try) the most conservative, synchronous, one-clock,
reset-everything, style I can muster.  However, when I go to Synthesize, I
find my simulations reveal *missing bits* and funny unknown values in the
middle of perfectly good vectors?!  Initially, ViewLogic confessed there was
a bug in their Schematic Generator (ViewGen) which did, in fact, "loose" bits,
but that the core synthesized netlist was OK, so "don't worry".  Well, I'm
still seeing the problem.  I'm begining to question the synthesizer!

Anyone else have similar experiences?  Is the XC4000 technology new for their
synthesizer, or something?  Or maybe, I'm doing something wrong...  I'd
appreciate any war stories..

Thomas A. Coonan
Scientific Atlanta, Network Systems Group

(770)903-2256



Wed, 22 Apr 1998 03:00:00 GMT  
 Synthesizer Bug? ViewLogic, VHDL, and XC4000


writes:

Quote:
> Path:
> Hello,

> I'm using ViewLogic's WorkView PLUS 5.2 on a pentium.  Using VHDL for an
> XC400x digital modem design.  I'm new to their tools, but have found the VHDL
> and simulation methodology to be a FANTASTIC time advantage for me.  
> Anyway,I find that my VHDL models simulate very predictable behaviorally.  I
> use (at least I try) the most conservative, synchronous, one-clock,
> reset-everything, style I can muster.  However, when I go to Synthesize, I
> find my simulations reveal *missing bits* and funny unknown values in the
> middle of perfectly good vectors?!  Initially, ViewLogic confessed there was
> a bug in their Schematic Generator (ViewGen) which did, in fact, "loose"
bits,
> but that the core synthesized netlist was OK, so "don't worry".  Well, I'm
> still seeing the problem.  I'm begining to question the synthesizer!

> Anyone else have similar experiences?  Is the XC4000 technology new for their
> synthesizer, or something?  Or maybe, I'm doing something wrong...  I'd
> appreciate any war stories..

I'm way behind on the Viewlogic stuff (switched to Galileo/VSystem last year,
used ProSeries with Actel as target before), but that simulation was solid.
However, after fitting and delay-backannotation you'd get all kinds of funny
things due to circuit instability. Tought me quite a bit about metastability.

If you could be a more specific about 'missing bits' and so on maybe I could
clarify.

Ben.



Sun, 03 May 1998 03:00:00 GMT  
 
 [ 2 post ] 

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