8-bit Shift Register VHDL Behavioral 
Author Message
 8-bit Shift Register VHDL Behavioral

Could someone please email me a copy of the above subject?  I am relatively
new to VHDL language.  I would like to simulate an 8-bit shift register.

Thank you very much.

Note:  Sorry for previous wrong post.



Sat, 31 Aug 1996 04:08:36 GMT  
 8-bit Shift Register VHDL Behavioral

Quote:
>Could someone please email me a copy of the above subject?  I am relatively
>new to VHDL language.  I would like to simulate an 8-bit shift register.

There are many ways to do a shift register depending on:

1.  simulation or synthesis is the major concern and what synthesis tool
2.  parallel or serial I/O, clock edge, synch or asynch reset or none.
3.  Use signals or variables
4.  Any special constructs are disallowed by tool such as 'generate'
5.  Logic type: bit, std_logic, etc
6.  bit numbering and direction
7.  Timing delays are used or not
8.  Shift enabl control signal or just free running on clock

Here is a serial in/parallel out, rising edge, right shifting,
 using signals, bit, async reset, free-running, probably synthesizable:

ENTITY shreg8 IS
  PORT (clock, ser_in, reset: IN bit;
        q_out: BUFFER bit_vector(7 DOWNTO 0)
       );
END;

ARCHITECTURE synth OF shreg8 IS
BEGIN
  PROCESS(clock, reset)
  BEGIN
    IF reset = '1' THEN
      q_out <= x"00";
    ELSIF clock'event AND clock = '1' THEN
      q_out <= ser_in & q_out(7 DOWNTO 1);
    END IF;
  END PROCESS;
END;



Sat, 31 Aug 1996 23:04:34 GMT  
 8-bit Shift Register VHDL Behavioral
: Could someone please email me a copy of the above subject?  I am relatively
: new to VHDL language.  I would like to simulate an 8-bit shift register.

: Thank you very much.

: Note:  Sorry for previous wrong post.

entity shiftreg8 is
  port ( nReset,
         Clk,
         Sin      : in   bit;
         Sout     : out  bit);
end shiftreg8;

architecture arch of shifreg8 is
  signal reg : bit_vector (7 downto 0);
begin

  Sout <= reg(7);

  shift : process (nReset, Clk)
  begin
    if (nReset='0') then
      reg <= "00000000";
    elsif (Clk'event and Clk='1') then
      reg(7 downto 1) <= reg(6 downto 0);
      reg(0)          <= Sin;
    end if;
  end process shift;
end arch;



Wed, 04 Sep 1996 10:48:42 GMT  
 8-bit Shift Register VHDL Behavioral
: Could someone please email me a copy of the above subject?  I am relatively
: new to VHDL language.  I would like to simulate an 8-bit shift register.

I would appreciate it very much if a copy is forwarded to me as well as I am aslo relatively new to VHDL language  Thanks




Sat, 07 Sep 1996 18:14:44 GMT  
 8-bit Shift Register VHDL Behavioral
I had sent this out to some people directly. I will also post this
here:
---
-- a very simple synthesizeable description of a shift register
entity shiftreg is
   generic (N    : Positive := 8); -- default value of N-bit shift register is 8
   port    (D    : in bit;         -- input to serial shift register
            CP   : in bit;         -- serial shift clock
            Q    : out bit         -- shift reg output
           );
end shiftreg;

architecture rtl of shiftreg is
  subtype word is bit_vector(N-1 downto 0);
  signal ssr : word;
begin
  -- define edges of shift register
  Q <= ssr(word'left);
  ssr(word'right) <= D;

  p_sync : process
  begin
    -- wait until rising_edge(CP);
    wait until CP'event and CP='1';
    for i in word'left downto (word'right + 1) loop
       ssr(i) <= ssr(i-1); -- perform the shift
    end loop;
  end process p_sync;
end rtl;
---------------------------------
Some code used to illustrate other concepts
---------------------------------
-- models a circular serial shift register
-- with parallel load
--
entity ssr is
  generic( N   : Positive := 4); -- length of shift register
  port( DATA   : in    bit_vector((n-1) downto 0); -- parallel load
        LD     : in    bit; -- parallel load enable
        CLK    : in    bit; -- shift clk
        SO     : out   bit
      );
end ssr;

--
-- modelled using conditional generate statements
use work.components.dff;
use work.components.muxnto1;
architecture struct of ssr is

constant N1    : Integer := (N-1);
signal   PO, PI   : bit_vector(N1 downto 0);

begin

--  the dff is a simple register with no unusual "edge" conditions
--  the mux has an "edge" condition for I = 0
--
g_shift : for i in 0 to N1 generate

   UDFF : dff
      port map( D => PI(i), CP => CLK, Q => PO(i), QN => open);

   g_0 : if I = 0 generate
      UMUX : muxnto1
        generic map(N => 2)
        port map( I(0) => PO(N1),
                  I(1) => DATA(i),
                  S(0) => LD,
                  Z    => PI(i)
                );
   end generate;

   g_12N1 : if I > 0 generate
      UMUX : muxnto1
        generic map(N => 2)
        port map( I(0) => PO(i-1),
                  I(1) => DATA(i),
                  S(0) => LD,
                  Z    => PI(i)
                );
   end generate;

end generate;
end struct;

--
-- modelled using just one generate
use work.components.dff;
use work.components.muxnto1;
architecture gen1 of ssr is

constant N1          : Integer := (N-1);
signal   PO, PI, SI  : bit_vector(N1 downto 0);

begin

--  the dff is a simple register with no unusual "edge" conditions
--  the mux has an "edge" condition for I = 0
--  this edge condition is handled using an additional signal
--
SI(N1 downto 1) <= PO((N1-1) downto 0);
SI(0) <= PO(N1);

g_shift : for i in 0 to N1 generate

   UDFF : dff
      port map( D => PI(i), CP => CLK, Q => PO(i), QN => open);

   UMUX : muxnto1
     generic map(N => 2)
     port map( I(0) => SI(i),
               I(1) => DATA(i),
               S(0) => LD,
               Z    => PI(i)
             );
end generate;
end gen1;
--
-- modelled without components
architecture dataflow of ssr is

constant N1          : Integer := (N-1);
signal   PO, PI, SI  : bit_vector(N1 downto 0);

begin

--  any concurrent statement may be replicated using a generate
SI(N1 downto 1) <= PO((N1-1) downto 0);
SI(0) <= PO(N1);

g_shift : for i in 0 to N1 generate

   b_dff : block
   begin
      seq : process
      begin
         wait until CLK'event and CLK='1';
         PO(i) <= PI(i);
      end process seq;
   end block b_dff;

   s_mux : PI(i) <= DATA(i) when (LD = '1') else
                    SI(i);
end generate;
end dataflow;
--
-- however let's not get ridiculous
architecture simple of ssr is

constant N1       : Integer := (N-1);
signal   PO, PI, SI          : bit_vector(N1 downto 0);

begin

--  any concurrent statement may be replicated using a generate
SI(N1 downto 1) <= PO((N1-1) downto 0);
SI(0) <= PO(N1);

s_mux : PI <= DATA when (LD = '1') else
              SI;

s_seq : PO <= PI when (not CLK'stable and CLK='1') else
              PO; -- unaffected in '93
end simple;

---
*****************************************************************
Prasad Paranjpe                    Snail Mail:
LSI Logic - US Engineering         1551 McCarthy
(408) 433-4370                     Milpitas, CA.

*****************************************************************



Wed, 11 Sep 1996 09:17:40 GMT  
 8-bit Shift Register VHDL Behavioral


writes:

Quote:
>---
>-- a very simple synthesizeable description of a shift register
>entity shiftreg is
>   generic (N    : Positive := 8); -- default value of N-bit shift register is 8
>   port    (D    : in bit;         -- input to serial shift register
>            CP   : in bit;         -- serial shift clock
>            Q    : out bit         -- shift reg output
>           );
>end shiftreg;

>architecture rtl of shiftreg is
>  subtype word is bit_vector(N-1 downto 0);
>  signal ssr : word;
>begin
>  -- define edges of shift register
>  Q <= ssr(word'left);
>  ssr(word'right) <= D;

>  p_sync : process
>  begin
>    -- wait until rising_edge(CP);
>    wait until CP'event and CP='1';
>    for i in word'left downto (word'right + 1) loop
>       ssr(i) <= ssr(i-1); -- perform the shift
>    end loop;
>  end process p_sync;
>end rtl;

I have a question about this model.  The line

  ssr(word'right) <= D;

is a concurrent signal assignment statement, which means that it executes
every time D changes and not on the rising edge of CP.  My question is, is this
what was intended?

If not, I think a better way of writing the architecture is:

architecture rtl of shiftreg is
  subtype word is bit_vector(N-1 downto 0);
  signal ssr : word;
begin

  Q <= ssr(word'left);

  p_sync : process
  begin
    wait until CP='1';
    ssr <= ssr (word'left - 1 downto word'right) & D;
  end process p_sync;
end rtl;

Or did I miss something?

--Paul

--
Paul Menchini

2 Davis Dr./POB 13036|    voice: 919-990-9506    |*PLEASE NOTE NEW EMAIL ADDR.*
RTP, NC  27709-3036  |    fax:   919-990-9507    |* THE OLD ONE DIES 1 May 94!*
---------------------+---------------------------+*****************************
Temporarily at:     Digital Equipment Corporation

                    508-486-7448



Fri, 13 Sep 1996 22:54:22 GMT  
 8-bit Shift Register VHDL Behavioral

Quote:


>writes:
>>---

The method suggested by Paul Menchini is clearly more concise but I do believe
that the block is functional. Since the signal ssr(word'right) does not leave
the shift register (only ssr(word'left) is connected to Q) the code should work
but this is a moot point at best since the alternative architecture is better.

-- Prasad

*****************************************************************
Prasad Paranjpe                    Snail Mail:
LSI Logic - US Engineering         1551 McCarthy
(408) 433-4370                     Milpitas, CA.

*****************************************************************



Sat, 14 Sep 1996 15:01:00 GMT  
 8-bit Shift Register VHDL Behavioral
I'm sure that there's many ways to create a behavorial shift
register.  Here's my $.02 worth from a previous design that
should synthesize fairly well (it worked in our environment).  
'Course your mileage may various with various compilers.  :^)

        -Gregg

    -- example of loadable 8-bit shift register
    -- [assumes that load and shift are mutually exclusive]

    SHIFTOUT_PROC:
    process (reset_n, clk)
    begin
        if reset_n='0' then
            shiftout <= "00000000";
        elsif clk'event and clk='1' then
            if shift_load='1' then   -- Load shiftout register
                shiftout(7 downto 0) <= tobeloaded(7 downto 0);
            elsif shift_en='1' then
                xmit_shiftout: for i in 1 to 7 loop
                    shiftout(i-1) <= shiftout(i);
                end loop xmit_shiftout;
                shiftout(7) <= '1';  -- serial in
            end if;
        end if;
    end process;

---

 ----------------------------------------------------------
 Gregg Lahti
 VLSI Technology, Inc.  [Portable Systems Division]

 sneakernet: 8375 S. River Parkway, MS 290, Tempe, AZ 85284
 ----------------------------------------------------------



Tue, 17 Sep 1996 02:03:11 GMT  
 8-bit Shift Register VHDL Behavioral
: I'm sure that there's many ways to create a behavorial shift
: register. ...
:
: 'Course your mileage may various with various compilers.  :^)
:  

No kidding... so can anyone synthesize it without the loop? I know the
Metamor compiler (aka: Data I/O VHDL-Direct) can handle something
like this:

     SHIFTOUT_PROC:
     process (reset_n, clk)
     begin
         if reset_n='0' then
             shiftout <= "00000000";
         elsif clk'event and clk='1' then
             if shift_load='1' then   -- Load shiftout register
                 shiftout(7 downto 0) <= tobeloaded(7 downto 0);
             elsif shift_en='1' then
                 shiftout <= '1' & shiftout(0 to 6);
             end if;
         end if;
     end process;

                                        - David Pellerin
                                          Duvall, Washington

                                          (206) 788-6397



Sun, 22 Sep 1996 07:16:33 GMT  
 
 [ 9 post ] 

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