8-bit Shift Register VHDL Behavioral
I had sent this out to some people directly. I will also post this
here:
---
-- a very simple synthesizeable description of a shift register
entity shiftreg is
generic (N : Positive := 8); -- default value of N-bit shift register is 8
port (D : in bit; -- input to serial shift register
CP : in bit; -- serial shift clock
Q : out bit -- shift reg output
);
end shiftreg;
architecture rtl of shiftreg is
subtype word is bit_vector(N-1 downto 0);
signal ssr : word;
begin
-- define edges of shift register
Q <= ssr(word'left);
ssr(word'right) <= D;
p_sync : process
begin
-- wait until rising_edge(CP);
wait until CP'event and CP='1';
for i in word'left downto (word'right + 1) loop
ssr(i) <= ssr(i-1); -- perform the shift
end loop;
end process p_sync;
end rtl;
---------------------------------
Some code used to illustrate other concepts
---------------------------------
-- models a circular serial shift register
-- with parallel load
--
entity ssr is
generic( N : Positive := 4); -- length of shift register
port( DATA : in bit_vector((n-1) downto 0); -- parallel load
LD : in bit; -- parallel load enable
CLK : in bit; -- shift clk
SO : out bit
);
end ssr;
--
-- modelled using conditional generate statements
use work.components.dff;
use work.components.muxnto1;
architecture struct of ssr is
constant N1 : Integer := (N-1);
signal PO, PI : bit_vector(N1 downto 0);
begin
-- the dff is a simple register with no unusual "edge" conditions
-- the mux has an "edge" condition for I = 0
--
g_shift : for i in 0 to N1 generate
UDFF : dff
port map( D => PI(i), CP => CLK, Q => PO(i), QN => open);
g_0 : if I = 0 generate
UMUX : muxnto1
generic map(N => 2)
port map( I(0) => PO(N1),
I(1) => DATA(i),
S(0) => LD,
Z => PI(i)
);
end generate;
g_12N1 : if I > 0 generate
UMUX : muxnto1
generic map(N => 2)
port map( I(0) => PO(i-1),
I(1) => DATA(i),
S(0) => LD,
Z => PI(i)
);
end generate;
end generate;
end struct;
--
-- modelled using just one generate
use work.components.dff;
use work.components.muxnto1;
architecture gen1 of ssr is
constant N1 : Integer := (N-1);
signal PO, PI, SI : bit_vector(N1 downto 0);
begin
-- the dff is a simple register with no unusual "edge" conditions
-- the mux has an "edge" condition for I = 0
-- this edge condition is handled using an additional signal
--
SI(N1 downto 1) <= PO((N1-1) downto 0);
SI(0) <= PO(N1);
g_shift : for i in 0 to N1 generate
UDFF : dff
port map( D => PI(i), CP => CLK, Q => PO(i), QN => open);
UMUX : muxnto1
generic map(N => 2)
port map( I(0) => SI(i),
I(1) => DATA(i),
S(0) => LD,
Z => PI(i)
);
end generate;
end gen1;
--
-- modelled without components
architecture dataflow of ssr is
constant N1 : Integer := (N-1);
signal PO, PI, SI : bit_vector(N1 downto 0);
begin
-- any concurrent statement may be replicated using a generate
SI(N1 downto 1) <= PO((N1-1) downto 0);
SI(0) <= PO(N1);
g_shift : for i in 0 to N1 generate
b_dff : block
begin
seq : process
begin
wait until CLK'event and CLK='1';
PO(i) <= PI(i);
end process seq;
end block b_dff;
s_mux : PI(i) <= DATA(i) when (LD = '1') else
SI(i);
end generate;
end dataflow;
--
-- however let's not get ridiculous
architecture simple of ssr is
constant N1 : Integer := (N-1);
signal PO, PI, SI : bit_vector(N1 downto 0);
begin
-- any concurrent statement may be replicated using a generate
SI(N1 downto 1) <= PO((N1-1) downto 0);
SI(0) <= PO(N1);
s_mux : PI <= DATA when (LD = '1') else
SI;
s_seq : PO <= PI when (not CLK'stable and CLK='1') else
PO; -- unaffected in '93
end simple;
---
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Prasad Paranjpe Snail Mail:
LSI Logic - US Engineering 1551 McCarthy
(408) 433-4370 Milpitas, CA.
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