Fast Fault Simulation 
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 Fast Fault Simulation

Fault-Simulation - Turbo Fault

High Performance Fault Simulator:

TurboFault combines high performance, versatility and accuracy. It is
highly competitive with hardware accelerators for classical test
fault grading. It supports synchronous and asynchronous designs at the
gate-level, including tri-state gates, latches, flip-flops, single and
multi-port RAMS, complex bus resolution functions, and USER Defined
primitives (UDPs). TurboFault reads Verilog gate-level netlists, and will
also read Standard Delay Format (SDF) timing files.

Advanced Cached-Concurrent Algorithm:

Turbofault utilizes a new algorithm optimed for today's computer
hardware that maximizes the simulation power of workstations. Syntest
Cached-Concurrent algorithm eliminates needless operations and with new
Fast Queque technology combines the best of unit delay and cycle-based
capabilities. No other fault simulator, hardware or software, matches the
performance of TurboFault.

TurboFault makes fault simulation an integral design tool for generating
a quality manufacturing test set. TurboFault supports single timing delay
for simulation accuracy and flexibility, without sacrificing speed.

TurboFault is the fastest concurrent fault simulator based on the latest
advances in cycle-based simulation technology. It simulates even *faster*
than existing expensive hardware accelerated fault simulators. Fault
simulation also consumes memory very quickly, so memory management is
critical. TurboFault combines efficient memory management with special
fault handling resulting in low memory consumption.

To hear more of Turbo-Fault, please send an e-mail to

and fax #.


The staff at Syntest Technology.

Tue, 04 Apr 2000 03:00:00 GMT  
 [ 1 post ] 

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