Internal nodes of an XOR tree 
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 Internal nodes of an XOR tree

I have created an xor tree using a recursive entity and generic (e.g.,
512 bits). However, I want to access every node in the tree in a
generic fashion in VHDL (depending on the size of the tree). Could
anyone help me in accessing every node in the tree?
Thanks in advance
 Here a piece of the code

entity xor_tree is
 generic (height: positive:= 512);
 port (input: in std_ulogic_vector(2**height-1 downto 0);
       output: out std_ulogic);
end entity xor_tree;

architecture recursive of xor_tree is
 signal bottom_output, top_output: std_ulogic;
 BASE: if height = 1 generate
  output <= input(1) xor input(0);
 end generate;

 SUBTREE: if height > 1 generate
  BOTTOM_TREE: component xor_tree
  generic map (height => (height - 1))
  port map (input => input(2**height-1 downto 2**(height-1)),
            output => bottom_output);

  TOP_TREE: component xor_tree
  generic map (height => (height - 1))
  port map (input => input(2**(height-1)-1 downto 0),
            output => top_output);

  output <= bottom_output xor top_output;
 end generate;

end architecture recursive;

Sat, 11 Dec 2004 00:18:28 GMT  
 [ 1 post ] 

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