finite state machines, state cad 
Author Message
 finite state machines, state cad

Hi. Any folks with experience using state cad tool for generating
state machines?  I have been doing manually, coding from a hand-drawn
state flow. Not great for configuration control, and does take some
editing labor.

My initial impression with tool is positive. Any other inputs
appreciated, pro or con.

Thanks.

Jim



Sat, 21 Jul 2001 03:00:00 GMT  
 finite state machines, state cad
Quote:

> Hi. Any folks with experience using state cad tool for generating
> state machines?  I have been doing manually, coding from a hand-drawn
> state flow. Not great for configuration control, and does take some
> editing labor.

> My initial impression with tool is positive. Any other inputs
> appreciated, pro or con.

I had to evaluate StateCad and my first impression was also positive.
But after using StateCad for a while I decided it beeing absolutely
unusable. It produced non-synthesizable VHDL-"Code" and the syntax is roughly
inconsistent and far away from VHDL. The VHDL produced by the tool is long,
hard to read and it produces very strange constructs. So I killed it from the
HDD. I'm doing well with a good VHDL-Syntax-Checking editor, such as xemacs or
nedit, and my silly brains - producing understandable, synthesizable VHDL-Code.
If You really need a tool for graphical VHDL I strongly recommend VeriBest which
is evaluated at our institute at the moment and considered a good, stable and
well-concepted tool.

Yours,
Osama Abu-Aish



Sat, 21 Jul 2001 03:00:00 GMT  
 finite state machines, state cad

Quote:

> Hi. Any folks with experience using state cad tool for generating
> state machines?  I have been doing manually, coding from a hand-drawn
> state flow. Not great for configuration control, and does take some
> editing labor.

I have been using Renoir from mentor for a while.
It has some good features but you can't trust the program fully. You
must check your generated code so you really got what you wanted.
Especially for statemachines i must say. You must draw your machines in
a certain way to not get latches and so on.
But when you learned the tricks it is a very fast tool to generate
statemachines with.
Actually I only use Renoir to make FSM and to generate the top level
(that boring component instantiation that it is so easy to do errors
in...). The rest of the code I code by hand.

Best regards,

Peter

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Sat, 21 Jul 2001 03:00:00 GMT  
 finite state machines, state cad
I have also used StateCad and I have to totally agree with Osama about
it's unusable code. Currently I am the only one in our company that uses
it, and then it is only infrequently to create diagrams for embedding in
module specifications.

Also, I understand from our internal EDA Computer Support guy that their
customer support after the sale is terrible.

Quote:

> I had to evaluate StateCad and my first impression was also positive.
> But after using StateCad for a while I decided it beeing absolutely
> unusable. It produced non-synthesizable VHDL-"Code" and the syntax is roughly
> inconsistent and far away from VHDL. The VHDL produced by the tool is long,
> hard to read and it produces very strange constructs. So I killed it from the
> HDD. I'm doing well with a good VHDL-Syntax-Checking editor, such as xemacs or
> nedit, and my silly brains - producing understandable, synthesizable VHDL-Code.
> If You really need a tool for graphical VHDL I strongly recommend VeriBest which
> is evaluated at our institute at the moment and considered a good, stable and
> well-concepted tool.

> Yours,
> Osama Abu-Aish

--
Brian C. Boorman
Harris RF Communications
Rochester, NY 14610

<Remove the XYZ. for valid address>


Sun, 22 Jul 2001 03:00:00 GMT  
 finite state machines, state cad

Quote:

> Hi. Any folks with experience using state cad tool for generating
> state machines?  I have been doing manually, coding from a hand-drawn
> state flow. Not great for configuration control, and does take some
> editing labor.

> My initial impression with tool is positive. Any other inputs
> appreciated, pro or con.

> Thanks.

> Jim

I have used it regularly at work for the last year or so and quite like
it. I create the state machines in Statecad and feed the VHDL output
into Xilinx Foundation schematics as macros. The latest Foundation 1.5
release has its own inbuilt state entry tool, but I prefer Statecad -
what I'm used to I guess.

It does have a couple of quirks. If "full vector" support is turned on,
the output becomes incredibly large - as reported in an earlier reply by
Osama Abu-Aish. I have also failed to implement counters in any sensible
way. I usually code in a one-hot style, as I am targeting FPGAs, but
there are occasions when I want to sit in a particular state for a fixed
number of clocks before transitioning to the next state. I have tried
putting counters in to the state as well as using a state bit to enable
another small counter state machine, and then feeding the terminal count
from that back to the original machine, but in order to get the counters
to work I have to enable full vector support and the output blows up to
many hundreds of extra lines of code. I've got around the problem by
bringing out counter enables to the schematic and feeding schematic
based counter TCs back in as inputs (VHDL purists feel free to puke )
Statecad's output formatting for the VHDL source could also be a bit
more readable. It creates a long string of embedded ANDs and ORs for the
next_STATE_n equations. If it started each OR term on a new line,
appropriately indented, it would be a lot easier to read.

Despite the above niggles it does the job for me. I previously had to
implement state machines in Viewdraw schematic. Ie draw them out by hand
on paper, hand code and minimise, then implement as a sea of AND/OR
gates feeding banks of DFFs. It could become a nightmare to support.
After trying to fix an inadvertant "feature" in one 3 year old design,
only about 30 states spread over about 10 sheets of schematic, I
eventually gave up trying to work out what was going on, re entered the
whole design in Statecad/Foundation and had it running correctly in 2
days. On my latest couple of projects I reckon I've been close to an
order of magnitude more productive with Statecad/Foundation than I was
previously with just Viewdraw. Your mileage may vary.

Jeff



Mon, 23 Jul 2001 03:00:00 GMT  
 finite state machines, state cad
This sounds like the approach I am taking.  Thanks for full vector
support tip.
I guess if you do not have it on you need to spell out each bit
and can't have an equation in bubble like CNT=3; You would need
CNT1=1 & CNT0=1;  That is the trade, correct?
The blowing up of output with vector on, does this cause synthesis
issues?  I noticed the wrapper it puts around with full vector
support really does not benefit me when porting the edif over
to Mentor.

Thanks.

Jim

Quote:


> > Hi. Any folks with experience using state cad tool for generating
> > state machines?  I have been doing manually, coding from a hand-drawn
> > state flow. Not great for configuration control, and does take some
> > editing labor.

> > My initial impression with tool is positive. Any other inputs
> > appreciated, pro or con.

> > Thanks.

> > Jim

> I have used it regularly at work for the last year or so and quite like
> it. I create the state machines in Statecad and feed the VHDL output
> into Xilinx Foundation schematics as macros. The latest Foundation 1.5
> release has its own inbuilt state entry tool, but I prefer Statecad -
> what I'm used to I guess.

> It does have a couple of quirks. If "full vector" support is turned on,
> the output becomes incredibly large - as reported in an earlier reply by
> Osama Abu-Aish. I have also failed to implement counters in any sensible
> way. I usually code in a one-hot style, as I am targeting FPGAs, but
> there are occasions when I want to sit in a particular state for a fixed
> number of clocks before transitioning to the next state. I have tried
> putting counters in to the state as well as using a state bit to enable
> another small counter state machine, and then feeding the terminal count
> from that back to the original machine, but in order to get the counters
> to work I have to enable full vector support and the output blows up to
> many hundreds of extra lines of code. I've got around the problem by
> bringing out counter enables to the schematic and feeding schematic
> based counter TCs back in as inputs (VHDL purists feel free to puke )
> Statecad's output formatting for the VHDL source could also be a bit
> more readable. It creates a long string of embedded ANDs and ORs for the
> next_STATE_n equations. If it started each OR term on a new line,
> appropriately indented, it would be a lot easier to read.

> Despite the above niggles it does the job for me. I previously had to
> implement state machines in Viewdraw schematic. Ie draw them out by hand
> on paper, hand code and minimise, then implement as a sea of AND/OR
> gates feeding banks of DFFs. It could become a nightmare to support.
> After trying to fix an inadvertant "feature" in one 3 year old design,
> only about 30 states spread over about 10 sheets of schematic, I
> eventually gave up trying to work out what was going on, re entered the
> whole design in Statecad/Foundation and had it running correctly in 2
> days. On my latest couple of projects I reckon I've been close to an
> order of magnitude more productive with Statecad/Foundation than I was
> previously with just Viewdraw. Your mileage may vary.

> Jeff



Mon, 23 Jul 2001 03:00:00 GMT  
 finite state machines, state cad
Jim,

    You could try this product named BetterState:

 BetterState .   It generates code for several languages.

Best regards,
Wiggo.

Quote:

> Hi. Any folks with experience using state cad tool for generating
> state machines?  I have been doing manually, coding from a hand-drawn
> state flow. Not great for configuration control, and does take some
> editing labor.

> My initial impression with tool is positive. Any other inputs
> appreciated, pro or con.

> Thanks.

> Jim

--
+---------------------------------------------------------------+
| Wiggo Olufsen                                                 |
| Cypress Software AS           Phone : +47-73-52 46 59         |
| P.O.Box 2668                  Fax   : +47-73-52 46 80         |

| NORWAY                                                        |
+---------------------------------------------------------------+


Tue, 24 Jul 2001 03:00:00 GMT  
 finite state machines, state cad
The link to BetterState is:  http://www.isi.com/Products/BetterState/.

There is a free lite version for download.

Quote:

> Jim,

>     You could try this product named BetterState:

>  BetterState .   It generates code for several languages.

> Best regards,
> Wiggo.


> > Hi. Any folks with experience using state cad tool for generating
> > state machines?  I have been doing manually, coding from a hand-drawn
> > state flow. Not great for configuration control, and does take some
> > editing labor.

> > My initial impression with tool is positive. Any other inputs
> > appreciated, pro or con.

> > Thanks.

> > Jim

> --
> +---------------------------------------------------------------+
> | Wiggo Olufsen                                                 |
> | Cypress Software AS           Phone : +47-73-52 46 59         |
> | P.O.Box 2668                  Fax   : +47-73-52 46 80         |

> | NORWAY                                                        |
> +---------------------------------------------------------------+

--
+---------------------------------------------------------------+
| Wiggo Olufsen                                                 |
| Cypress Software AS           Phone : +47-73-52 46 59         |
| P.O.Box 2668                  Fax   : +47-73-52 46 80         |

| NORWAY                                                        |
+---------------------------------------------------------------+


Tue, 24 Jul 2001 03:00:00 GMT  
 
 [ 8 post ] 

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