std_logic_1164 
Author Message
 std_logic_1164

Dear VHDL Professionals :

Attached is the latest ballot version std_logic_1164 VHDL package. This is
identical to the package being ballotted by the IEEE VHDL Model Standards
Group under PAR 1164.

Note to CAE Vendors : We appreciate all the support you have provided to the
IEEE in helping to establish this model interface standard. We ask that each
of you support this package without modification of the package declaration.
You may modify the implementation of the package body to the slight degree
you may find necessary to support your current implementation ( ie. variables
instead of aliases ). Please do not change the semantics of the implementations
as this will confuse the end users. Also, do not attempt to create your own
type names (ie. MVL9 instead of std_ulogic ) as this will also confuse the
end users and render the implementation non-compliant. You may, however, create
your own subtypes of the 9-state system if this helps you support certain
hardware acceleration, hardware modelers, internal optimized types, etc.
(ie. Subtype MVL7 is std_ulogic range 'X' to 'H' ). It is important that
port level type matching be preserved implicitly without type conversions.

If I may be of any assistance regarding the package, please call or
preferrably email your questions.

Sincerely,

-------------------------------------------------------------
William Billowitch                   e-mail: uunet!vhdl!wdb

974 Marcon Blvd, Suite 260           Phone : 215-266-9791
Allentown, PA 18103                  Fax   : 215-266-9783

================================= cut ======================================

-- --------------------------------------------------------------------
--
--   File name :  std_logic_1164.pkg.vhdl
--   Title     :  Std_Logic_1164 multi-value logic system interface package
--   Library   :  IEEE
--   Author(s) :  W. Billowitch ( The VHDL Consulting Group )
--   Purpose   :  This packages defines a standard for digital designers
--             :  to use in describing the interconnection data types
--             :  used in modeling common ttl, cmos, GaAs, nmos,
--             :  pmos, and ecl digital devices.
--             :
--   Limitation:  The logic system defined in this package may
--             :  be insufficient for modeling switched transistors,
--             :  since that requirement is out of the scope of this
--             :  effort.
--             :
--   Notation  :  No other declarations or definitions shall be included
--             :  in this package. Any additional declarations shall be
--             :  placed in other orthogonal packages ( ie. timing, etc )
--             :
-- --------------------------------------------------------------------
--   Modification History :
-- --------------------------------------------------------------------
--   Version No:| Author:|  Mod. Date:| Changes Made:
--     v4.000   |  wdb   |   6/24/91  | Std_logic_1164 Ballot Source Code
-- --------------------------------------------------------------------
-- Library IEEE; -- proposed location of this package
-- --------------------------------------------------------------------

PACKAGE Std_Logic_1164 is

    -------------------------------------------------------------------    
    -- Logic State System  (unresolved)
    -------------------------------------------------------------------    
    TYPE std_ulogic is ( 'U',  -- Unitialized
                         'X',  -- Forcing  0 or 1
                         '0',  -- Forcing  0
                         '1',  -- Forcing  1
                         'Z',  -- High Impedance  
                         'W',  -- Weak     0 or 1
                         'L',  -- Weak     0       ( for ECL open emitter )
                         'H',  -- Weak     1       ( for open Drain or Collector )
                         '-'   -- don't care
                       );
    -------------------------------------------------------------------    
    -- Unconstrained array of std_ulogic for use with the resolution function
    -------------------------------------------------------------------    
    TYPE std_ulogic_vector IS ARRAY ( NATURAL RANGE <> ) of std_ulogic;

    -------------------------------------------------------------------    
    -- Resolution function
    -------------------------------------------------------------------    
    FUNCTION resolved ( s : std_ulogic_vector ) RETURN std_ulogic;

    -------------------------------------------------------------------    
    -- *** Industry Standard Logic Type ***
    -------------------------------------------------------------------    
    SUBTYPE std_logic IS resolved std_ulogic;

    -------------------------------------------------------------------    
    -- Unconstrained array of std_logic for use in declaring signal arrays
    -------------------------------------------------------------------    
    TYPE std_logic_vector IS ARRAY ( NATURAL RANGE <>) of std_logic;

    -------------------------------------------------------------------    
    -- Basic states + Test
    -------------------------------------------------------------------    
    SUBTYPE X01   is resolved std_ulogic range 'X' to '1'; -- ('X','0','1')
    SUBTYPE X01Z  is resolved std_ulogic range 'X' to 'Z'; -- ('X','0','1','Z')
    SUBTYPE UX01  is resolved std_ulogic range 'U' to '1'; -- ('U','X','0','1')
    SUBTYPE UX01Z is resolved std_ulogic range 'U' to 'Z'; -- ('U','X','0','1','Z')

    -------------------------------------------------------------------    
    -- Overloaded Logical Operators
    -------------------------------------------------------------------    

    FUNCTION "and"  ( l : std_ulogic; r : std_ulogic ) RETURN UX01;
    FUNCTION "nand" ( l : std_ulogic; r : std_ulogic ) RETURN UX01;
    FUNCTION "or"   ( l : std_ulogic; r : std_ulogic ) RETURN UX01;
    FUNCTION "nor"  ( l : std_ulogic; r : std_ulogic ) RETURN UX01;
    FUNCTION "xor"  ( l : std_ulogic; r : std_ulogic ) RETURN UX01;
    FUNCTION "not"  ( l : std_ulogic                 ) RETURN UX01;

    -------------------------------------------------------------------    
    -- Vectorized Overloaded Logical Operators
    -------------------------------------------------------------------    
    FUNCTION "and"  ( l, r : std_logic_vector ) RETURN std_logic_vector;
    FUNCTION "nand" ( l, r : std_logic_vector ) RETURN std_logic_vector;
    FUNCTION "or"   ( l, r : std_logic_vector ) RETURN std_logic_vector;
    FUNCTION "nor"  ( l, r : std_logic_vector ) RETURN std_logic_vector;
    FUNCTION "xor"  ( l, r : std_logic_vector ) RETURN std_logic_vector;
    FUNCTION "not"  ( l    : std_logic_vector ) RETURN std_logic_vector;

    FUNCTION "and"  ( l, r : std_ulogic_vector ) RETURN std_ulogic_vector;
    FUNCTION "nand" ( l, r : std_ulogic_vector ) RETURN std_ulogic_vector;
    FUNCTION "or"   ( l, r : std_ulogic_vector ) RETURN std_ulogic_vector;
    FUNCTION "nor"  ( l, r : std_ulogic_vector ) RETURN std_ulogic_vector;
    FUNCTION "xor"  ( l, r : std_ulogic_vector ) RETURN std_ulogic_vector;
    FUNCTION "not"  ( l    : std_ulogic_vector ) RETURN std_ulogic_vector;

    -------------------------------------------------------------------    
    -- Conversion Functions ( strips strength from buses + signals )
    -------------------------------------------------------------------    
    FUNCTION Convert_to_X01  ( s : std_logic_vector ) RETURN  std_logic_vector;
    FUNCTION Convert_to_X01  ( s : std_ulogic_vector) RETURN  std_ulogic_vector;
    FUNCTION Convert_to_X01  ( s : std_ulogic       ) RETURN  X01;
    FUNCTION Convert_to_X01  ( b : bit_vector       ) RETURN  std_logic_vector;
    FUNCTION Convert_to_X01  ( b : bit_vector       ) RETURN  std_ulogic_vector;
    FUNCTION Convert_to_X01  ( b : bit              ) RETURN  X01;      

    FUNCTION Convert_to_X01Z ( s : std_logic_vector ) RETURN  std_logic_vector;
    FUNCTION Convert_to_X01Z ( s : std_ulogic_vector) RETURN  std_ulogic_vector;
    FUNCTION Convert_to_X01Z ( s : std_ulogic       ) RETURN  X01Z;
    FUNCTION Convert_to_X01Z ( b : bit_vector       ) RETURN  std_logic_vector;
    FUNCTION Convert_to_X01Z ( b : bit_vector       ) RETURN  std_ulogic_vector;
    FUNCTION Convert_to_X01Z ( b : bit              ) RETURN  X01Z;      

    FUNCTION Convert_to_Bit  ( s : std_logic_vector ) RETURN  bit_vector;
    FUNCTION Convert_to_Bit  ( s : std_ulogic_vector) RETURN  bit_vector;
    FUNCTION Convert_to_Bit  ( s : std_ulogic       ) RETURN  bit;

    FUNCTION Convert_to_UX01 ( s : std_logic_vector ) RETURN  std_logic_vector;
    FUNCTION Convert_to_UX01 ( s : std_ulogic_vector) RETURN  std_ulogic_vector;
    FUNCTION Convert_to_UX01 ( s : std_ulogic       ) RETURN  UX01;

    -------------------------------------------------------------------    
    -- Edge Detection
    -------------------------------------------------------------------    
    FUNCTION rising_edge  (SIGNAL s : std_ulogic) RETURN boolean;
    FUNCTION falling_edge (SIGNAL s : std_ulogic) RETURN boolean;

END Std_Logic_1164;

-- --------------------------------------------------------------------
--
--   File name :  std_logic_1164.pkgbody.vhdl
--   Title     :  Std_Logic_1164 multi-value logic system interface package
--   Library   :  IEEE
--   Author(s) :  W. Billowitch ( The VHDL Consulting Group )
--   Purpose   :  This packages defines a standard for digital designers
--             :  to use in describing the interconnection data types
--             :  used in modeling common ttl, cmos, GaAs, nmos,
--             :  pmos, and ecl digital devices.
--             :
--   Limitation:  The logic system defined in this package may
--             :  be insufficient for
...

read more »



Mon, 20 Dec 1993 00:33:19 GMT  
 std_logic_1164

Quote:

>Dear VHDL Professionals :

>Attached is the latest ballot version std_logic_1164 VHDL package. This is
>identical to the package being ballotted by the IEEE VHDL Model Standards
>Group under PAR 1164.

   .
   .
   .
Quote:

>-- --------------------------------------------------------------------
>--
>--   File name :  std_logic_1164.pkg.vhdl
>--   Title     :  Std_Logic_1164 multi-value logic system interface package
>--   Library   :  IEEE
>--   Author(s) :  W. Billowitch ( The VHDL Consulting Group )

   .
   .
   .

Quote:
>-- --------------------------------------------------------------------
>--   Modification History :
>-- --------------------------------------------------------------------
>--   Version No:| Author:|  Mod. Date:| Changes Made:
>--     v4.000   |  wdb   |   6/24/91  | Std_logic_1164 Ballot Source Code
>-- --------------------------------------------------------------------
>-- Library IEEE; -- proposed location of this package
>-- --------------------------------------------------------------------

>PACKAGE Std_Logic_1164 is

>    -------------------------------------------------------------------    
>    -- Logic State System  (unresolved)
>    -------------------------------------------------------------------    
>    TYPE std_ulogic is ( 'U',  -- Unitialized
>                         'X',  -- Forcing  0 or 1
>                         '0',  -- Forcing  0
>                         '1',  -- Forcing  1
>                         'Z',  -- High Impedance  
>                         'W',  -- Weak     0 or 1
>                         'L',  -- Weak     0       ( for ECL open emitter )
>                         'H',  -- Weak     1       ( for open Drain or Collector )
>                         '-'   -- don't care
>                       );
>    -------------------------------------------------------------------    

Posted below is a copy of what i have recieved from our vendor.
In the revision history:

--     v2.300   |  wdb   |  10/24/90  | Changed '-' to 'D', deleted attributes

In this latest posting, the revision history has been omitted, but
evidently, the 'D' has changed back into a '-'.
Is this truly the case? Our vendor had said they had just recieved
our copy from Bill, and that it was the latest one...
   .
   .
   .

-- --------------------------------------------------------------------
--   Modification History :
-- --------------------------------------------------------------------
--   Version No:| Author:|  Mod. Date:| Changes Made:
--     v2.000   |  wdb   |   6/19/90  | DRAFT STANDARD
--     v2.100   |  wdb   |   7/16/90  | Addition of 'U' and '-' states
--     v2.200   |  wdb   |  10/08/90  | Modified 'U' propagation
--     v2.300   |  wdb   |  10/24/90  | Changed '-' to 'D', deleted attributes
--     v2.400   |  wdb   |  11/12/90  | Fixed subtyped subtypes
--     v2.500   |  wdb   |  01/02/91  | Change output types of overloaded operators
--     v2.600   |  wdb   |  01/04/91  | Clean UP
--     v2.700   |  wdb   |  01/08/91  | Add Conversion functions to Bit
--     v2.800   |  wdb   |  03/03/91  | Pre-Ballot Cleanup
-- --------------------------------------------------------------------
   .
   .
   .
    -------------------------------------------------------------------    
    -- Logic State System  (unresolved)
    -------------------------------------------------------------------    
    TYPE std_ulogic is ( 'U',  -- Unitialized
                         'X',  -- Forcing  0 or 1
                         '0',  -- Forcing  0
                         '1',  -- Forcing  1
                         'Z',  -- High Impedance  
                         'W',  -- Weak     0 or 1
                         'L',  -- Weak     0       ( for ECL open emitter )
                         'H',  -- Weak     1       ( for open Drain or Collector )
                         'D'   -- don't care
                       );

   .
   .
   .

--------------------------------------------------------------------
Robert D. Birch
Unisys
(Me? i'm confused. i don't know who my opinions represent...)
--------------------------------------------------------------------



Sun, 26 Dec 1993 23:31:29 GMT  
 
 [ 2 post ] 

 Relevant Pages 

1. Do I really need Std_Logic_1164 here?

2. Latest STD_LOGIC_1164 package

3. Std_Logic_1164

4. Use of '-' in std_logic_1164

5. ieee.std_logic_1164 neophyte question

6. ieee.std_logic_1164.vhdl

7. Do people use ieee.std_logic_1164 for tristate signals?

8. SUMMARY: Do people use ieee.std_logic_1164?

9. std_logic_1164...

10. Std_Logic_1164

11. std_logic_1164

12. std_logic_1164

 

 
Powered by phpBB® Forum Software