a problem with generate statement 
Author Message
 a problem with generate statement

Hi

I need to instantiate a component 64 times. I am using "generate" statement
to do that. However, when I map the components with corresponding
entity(architecture), I get the error that " Component is never instanced in
the corresponding set of statements". This is weird because I am
instantiating the component in generate statement.

I am attaching a simple equivalent of my code where I use generate statement
to instantiate a clock component twice. This gives the same error at line
55, which is:
        for all : CLOCK_GEN_C use entity work.CLOCK_GENERATOR(CLOCK_IMPL1);

I will appreciate any suggestions on this problem. I found some sample code
on net which uses generate statement, but I didn't see any difference. I am
using Synopsis VHDL analyzer version 2000.12-1.

Thanks.

Rajneesh

----------------------------------------------------------------------------
-----------------------------
--implementation of clock
library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity CLOCK_GENERATOR is
        generic(PER: Time);
        port( RESET: in Std_Logic; CLOCK: out Std_Logic);
end CLOCK_GENERATOR;

architecture CLOCK_IMPL1 of CLOCK_GENERATOR is
        signal CLK : Std_Logic;
begin
        process(RESET, CLK)
                variable CLKE : Std_Logic := '0';
        begin
                if RESET = '0' and not RESET'STABLE then
                        CLKE := '1';
                        CLK <= transport '0' after PER/2;
                        CLK <= transport '1' after PER;
                end if;
                if RESET = '1' and not RESET'STABLE then
                        CLKE := '0';
                end if;
                if CLK='1' and not CLK'STABLE and CLKE='1' then
                        CLK <= transport '0' after PER/2;
                        CLK <= transport '1' after PER;
                end if;
                CLOCK <= CLK;
        end process;
end CLOCK_IMPL1;

entity TEST_BENCH is

end TEST_BENCH;

library IEEE;
use IEEE.STD_LOGIC_1164.all;
use work.all;

architecture TEST_ARCH of TEST_BENCH is

        component CLOCK_GEN_C
                generic(PER: Time);
                port( RESET: in Std_Logic; CLOCK: out Std_Logic);
        end component;

        --make signals as arrays to ease port mappings etc
        signal  tCLK                           :  std_logic_vector(1 to 2);
        signal  tRESET                         :  std_logic_vector(1 to 2);

        for all : CLOCK_GEN_C use entity work.CLOCK_GENERATOR(CLOCK_IMPL1);

begin

        clkgen: for J in 1 to 2 generate
        MYCLK: CLOCK_GEN_C
                generic map(10 ns)
                port map( tRESET(J), tCLK(J));
        end generate clkgen;

end TEST_ARCH;



Fri, 21 Jan 2005 07:48:48 GMT  
 a problem with generate statement
Quote:
>I need to instantiate a component 64 times. I am using "generate" statement
>to do that. However, when I map the components with corresponding
>entity(architecture), I get the error that " Component is never instanced in
>the corresponding set of statements". This is weird because I am
>instantiating the component in generate statement.

>I am attaching a simple equivalent of my code where I use generate statement
>to instantiate a clock component twice. This gives the same error at line
>55, which is:
>        for all : CLOCK_GEN_C use entity work.CLOCK_GENERATOR(CLOCK_IMPL1);

>I will appreciate any suggestions on this problem. I found some sample code
>on net which uses generate statement, but I didn't see any difference. I am
>using Synopsis VHDL analyzer version 2000.12-1.

>Thanks.

>Rajneesh

I have several issues with the style of your code, which would have been
alleviated with teh use of emacs, and PORT COPY/PASTE AS TESTBENCH (a plug for
emacs).
1, You used a component declaration with a different name.  This is usually not
recommended unless absolutely needed.

Quote:
>entity CLOCK_GENERATOR is
>        generic(PER: Time);
>        port( RESET: in Std_Logic; CLOCK: out Std_Logic);
>end CLOCK_GENERATOR;

...
>architecture TEST_ARCH of TEST_BENCH is

>        component CLOCK_GEN_C
>                generic(PER: Time);
>                port( RESET: in Std_Logic; CLOCK: out Std_Logic);
>        end component;

2. You use a configuration specification.  I prefer configuration declaration
because they are more flexible (can have several of them).

3. THere is an error in your configuration.

Corrected code:
architecture TEST_ARCH of TEST_BENCH is

--   component CLOCK_GEN_C
--     generic(PER :    time);
--     port( RESET : in std_logic; CLOCK : out std_logic);
--   end component;
  component CLOCK_GENERATOR is
    generic (
      PER : time);
    port (
      RESET : in  std_logic;
      CLOCK : out std_logic);
  end component CLOCK_GENERATOR;

  --make signals as arrays to ease port mappings etc
  signal tCLK   : std_logic_vector(1 to 2);
  signal tRESET : std_logic_vector(1 to 2);

--   for all : CLOCK_GEN_C use entity work.CLOCK_GENERATOR(CLOCK_IMPL1);

begin

  clkgen : for J in 1 to 2 generate
--     MYCLK : CLOCK_GEN_C
--       generic map(10 ns)
--       port map( tRESET(J), tCLK(J));
    CLOCK_GENERATOR_1 : CLOCK_GENERATOR
      generic map (
        PER => 10 ns)                   -- [time]
      port map (
        RESET => tRESET(J),             -- [in  std_logic]
        CLOCK => tCLK(J));              -- [out std_logic]
  end generate clkgen;

end TEST_ARCH;

configuration C_cfg of TEST_BENCH is
  for TEST_ARCH
    for clkgen(1 to 2)
      for CLOCK_GENERATOR_1 : CLOCK_GENERATOR
        use entity work.CLOCK_GENERATOR(CLOCK_IMPL1);
      end for;
    end for;
  end for;
end configuration C_cfg;

--
the following also works if you want to use a different component name
(bad style, but...)
architecture TEST_ARCH of TEST_BENCH is

  component CLOCK_GEN_C
    generic(PER :    time);
    port( RESET : in std_logic; CLOCK : out std_logic);
  end component;

  --make signals as arrays to ease port mappings etc
  signal tCLK   : std_logic_vector(1 to 2);
  signal tRESET : std_logic_vector(1 to 2);

--   for all : CLOCK_GEN_C use entity work.CLOCK_GENERATOR(CLOCK_IMPL1);

begin

  clkgen : for J in 1 to 2 generate
--     MYCLK : CLOCK_GEN_C
--       generic map(10 ns)
--       port map( tRESET(J), tCLK(J));
    CLOCK_GENERATOR_1 : CLOCK_GEN_C
      generic map (
        PER => 10 ns)                   -- [time]
      port map (
        RESET => tRESET(J),             -- [in  std_logic]
        CLOCK => tCLK(J));              -- [out std_logic]
  end generate clkgen;

end TEST_ARCH;

configuration C_cfg of TEST_BENCH is
  for TEST_ARCH
    for clkgen(1 to 2)
      for CLOCK_GENERATOR_1 : CLOCK_GEN_C
        use entity work.CLOCK_GENERATOR(CLOCK_IMPL1);
      end for;
    end for;
  end for;
end configuration C_cfg;
%vcom -93 testc2.vhd
Model Technology ModelSim XE vcom 5.5b Compiler 2001.05 May 23 2001
-- Loading package standard
-- Loading package std_logic_1164
-- Compiling entity clock_generator
-- Compiling architecture clock_impl1 of clock_generator
-- Compiling entity test_bench
-- Compiling architecture test_arch of test_bench
WARNING[1]: testc2.vhd(65): No default binding for component: "clock_gen_c".
(No entity named "clock_gen_c" was found)
-- Compiling configuration c_cfg
-- Loading entity test_bench
-- Loading architecture test_arch of test_bench
-- Loading entity clock_generator
%
For those who wnat to dwell more into this, check uout my Coding Style book.
---------------------------------------------------------------------------
Ben Cohen     Publisher, Trainer, Consultant    (310) 721-4830  

Author of following textbooks:
* Real Chip Design and Verification Using Verilog and VHDL, 2002 isbn
0-9705394-2-8
* Component Design by Example ",  2001 isbn  0-9705394-0-1
* VHDL Coding Styles and Methodologies, 2nd Edition, 1999 isbn 0-7923-8474-1
* VHDL Answers to Frequently Asked Questions, 2nd Edition, isbn 0-7923-8115
------------------------------------------------------------------------------



Fri, 21 Jan 2005 11:46:00 GMT  
 a problem with generate statement
The problem is that the generate statement forms a separate scope or
sub-block. The configuration however is in the architecture, not the
sub-block and so does not bind the component to the entity (configurations
only apply to the current scope).

This is a well-known problem in VHDL - most users do not realise that a
generate statement is a separate sub-block.

In VHDL'93 you can add a declaration part to a generate statement:

  clkgen: for J in 1 to 2 generate
    for all : CLOCK_GEN_C use entity work.CLOCK_GENERATOR(CLOCK_IMPL1);
  begin
    MYCLK: CLOCK_GEN_C generic map(10 ns) port map( tRESET(J), tCLK(J));
  end generate clkgen;

However, many synthesis tools only really support the VHDL'87 standard which
doesn't allow this, so you need to add a block statement within the generate
and put the configuration there:

  clkgen: for J in 1 to 2 generate
    block
      for all : CLOCK_GEN_C use entity work.CLOCK_GENERATOR(CLOCK_IMPL1);
    begin
      MYCLK: CLOCK_GEN_C generic map(10 ns) port map( tRESET(J), tCLK(J));
    end block;
  end generate clkgen;

For a fuller explanation see my web page -
http://www.ecs.soton.ac.uk/~ajr1/ - follow link to the FAQ and it's question
12.
Andy
--
----------------------------
Andy Rushton
ECS Department
Southampton University

Quote:
> Hi

> I need to instantiate a component 64 times. I am using "generate"
statement
> to do that. However, when I map the components with corresponding
> entity(architecture), I get the error that " Component is never instanced
in
> the corresponding set of statements". This is weird because I am
> instantiating the component in generate statement.

> I am attaching a simple equivalent of my code where I use generate
statement
> to instantiate a clock component twice. This gives the same error at line
> 55, which is:
>         for all : CLOCK_GEN_C use entity

work.CLOCK_GENERATOR(CLOCK_IMPL1);
Quote:

> I will appreciate any suggestions on this problem. I found some sample
code
> on net which uses generate statement, but I didn't see any difference. I
am
> using Synopsis VHDL analyzer version 2000.12-1.

> Thanks.

> Rajneesh

> --------------------------------------------------------------------------
--
> -----------------------------
> --implementation of clock
> library IEEE;
> use IEEE.STD_LOGIC_1164.all;

> entity CLOCK_GENERATOR is
>         generic(PER: Time);
>         port( RESET: in Std_Logic; CLOCK: out Std_Logic);
> end CLOCK_GENERATOR;

> architecture CLOCK_IMPL1 of CLOCK_GENERATOR is
>         signal CLK : Std_Logic;
> begin
>         process(RESET, CLK)
>                 variable CLKE : Std_Logic := '0';
>         begin
>                 if RESET = '0' and not RESET'STABLE then
>                         CLKE := '1';
>                         CLK <= transport '0' after PER/2;
>                         CLK <= transport '1' after PER;
>                 end if;
>                 if RESET = '1' and not RESET'STABLE then
>                         CLKE := '0';
>                 end if;
>                 if CLK='1' and not CLK'STABLE and CLKE='1' then
>                         CLK <= transport '0' after PER/2;
>                         CLK <= transport '1' after PER;
>                 end if;
>                 CLOCK <= CLK;
>         end process;
> end CLOCK_IMPL1;

> entity TEST_BENCH is

> end TEST_BENCH;

> library IEEE;
> use IEEE.STD_LOGIC_1164.all;
> use work.all;

> architecture TEST_ARCH of TEST_BENCH is

>         component CLOCK_GEN_C
>                 generic(PER: Time);
>                 port( RESET: in Std_Logic; CLOCK: out Std_Logic);
>         end component;

>         --make signals as arrays to ease port mappings etc
>         signal  tCLK                           :  std_logic_vector(1 to
2);
>         signal  tRESET                         :  std_logic_vector(1 to
2);

>         for all : CLOCK_GEN_C use entity

work.CLOCK_GENERATOR(CLOCK_IMPL1);

- Show quoted text -

Quote:

> begin

>         clkgen: for J in 1 to 2 generate
>         MYCLK: CLOCK_GEN_C
>                 generic map(10 ns)
>                 port map( tRESET(J), tCLK(J));
>         end generate clkgen;

> end TEST_ARCH;



Fri, 21 Jan 2005 17:34:22 GMT  
 
 [ 3 post ] 

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