Don't cares in std_logic_vector 
Author Message
 Don't cares in std_logic_vector

Hi there,

after reading through the SYNOPSYS manual about the use of Don't Care 'D'
values in signals I get a bit confused about them.

In Simulation a statement like

signal bus : std_logic_vector(3 downto 0);

bus <= "0110";
if (bus = "0DD0") then
...

would always generate a FALSE for the comparison, because std_logic_vector
is just an enumeration data type.
But using it in synthesis the compiler reduces all signal values to '0' or
'1', so would that comparison become TRUE in that case ?

Thanks very much in advance,

Fabian
--
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Fabian Wolf                                   tel:  (++49-531) 391 3728

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Sun, 30 May 1999 03:00:00 GMT  
 Don't cares in std_logic_vector

Quote:

> Hi there,

> after reading through the SYNOPSYS manual about the use of Don't Care 'D'
> values in signals I get a bit confused about them.

> In Simulation a statement like

> signal bus : std_logic_vector(3 downto 0);

> bus <= "0110";
> if (bus = "0DD0") then
> ...

> would always generate a FALSE for the comparison, because std_logic_vector

Not always. Suppose the current value of bus is "0DD0", and you assign the
"0110" to this signal it will get that new after 1 delta delay. So
the comparision bus="0DD0" is true.
Only as a joke. But now really your problem.

In the std_logic_1164 package the the MVL9 is declared. The '-' is used for
don't care (probably the 'D' is used previously by Synopsys, I don't know?)

PACKAGE std_logic_1164 IS
  TYPE std_ulogic IS ...
  etc.

Indeed you would expect that '1'='-' will result in TRUE.
Since std_ulogic is a new type an implicit comparision function is declared
for this type. This implicit function has the expected behaviour:
  only if left and rigth operand have the same value the result is TRUE.
But '1'='-' are NOT the same so the result is false from a simulation point
of view. Your synthesys tool does interpreted it a don't care, hence the difference.

What is forgotten? It was better (I think) to have an explicit comparison
function in the std_logic_1164 package that describes the intended behaviour of '-'.
Since it is not in this package you could write your own comparision function. But
then you get al kinds of visibility problems.

E.g.
LIBRARY ieee;
USE ieee.std_logic_1164.ALL; -- contains the implicit "="
USE work.my_own.ALL; -- contains my own "="

If a and b are of type std_ulogic and you write
   a = b ? which functions should be taken? => hence an error message from the tool (I hope!)
You could explicitly point to your '=' like:  work.my_own."="(a,b)

The difference between simulation and synthesis is of course not nice. In the new
IEEE standard 1076.3 a function STD_MATCH (in the package numeric_std) is declared
that fixes that problem. E.g
   signal a : std_logic_vector(0 TO 3);
   std_match("1-1-",a) is true iff  a(0)='1' AND a(2)='1
(By the way is 1076.3 already an IEEE standard?)

Egbert Molenkamp
Dept. of Computer Science
University of Twente
PO Box 217
7500 AE  Enschede
the Netherlands



Tue, 01 Jun 1999 03:00:00 GMT  
 Don't cares in std_logic_vector


Quote:

>after reading through the SYNOPSYS manual about the use of Don't Care 'D'
>values in signals I get a bit confused about them.

I may get a lot of disagreement on this, but I believe that it is
preferrable to avoid
don't care because of AUTO-REGRESSION TESTS:
     Don't cares can cause results to stimulus which will
     vary from the RTL model.  Thus, when performing auto-regression tests
the
     verification task will become more difficult since the golden
verification results
     (MISR signature or file) may not match the one produced by the gate
level implementation version.

I understand that the use of don't care can yield a design with less
gates, and can potentially be faster.   In terms of gate area, a few more
gates, without the relatively insignificant area
reduction (relative the the FPGA or ASIC size), are worth the cost when
considering auto-regression tests.

In my latest book "VHDL Answers to FAQs" I discuss the issues of design
verification.

--=============================================
-- Ben Cohen, Hughes Aircraft Co,  RE- R1/B507
-- ** "VHDL Coding Styles and Methodologies",
--     ISBN 0-7923-9598-0  Kluwer Academic Publishers, 1995.
-- ** "VHDL Answers to Frequently Asked Questions"  
--     ISBN 0-7923-9791-6 Kluwer Academic Publishers, 1996.
-- FTP site:   users.aol.com       /vhdlcohen/vhdl
-- Web page:   http://members.aol.com/vhdlcohen/vhdl
-- (310) 334-7389,      fax: (310) 334-1749
--=============================================



Wed, 02 Jun 1999 03:00:00 GMT  
 
 [ 3 post ] 

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