Synthesizing RAM bank from VHDL? 
Author Message
 Synthesizing RAM bank from VHDL?

Hello everybody,

I'm currently writing a VHDL description of a Cache RAM. I intend to use it
as part of a microprocessor description, which I want to synthesize using
the Synopsys Design Compiler.

My problem is the following:
How can I tell Synopsys in VHDL to make a RAM bank (size about 30 kbyte,
should be variable) without having it try to optimize it (that would cost
far too much time, and would seem a bit pointless to me, RAM having such
a regular structure). I noticed the Designware RAMS shouldn't be bigger
than 256 bits, for just that reason (excessive compile times).

It says in the Designware components databook:
"If a large memory is required, use a
RAM hard macro if it is available in the ASIC library you are
using and use one of the DW03 FIFO controllers."

Sure, but can I use such a 'RAM hard macro' (whatever that is, probably
technology dependent) in my VHDL description? And yes, I _do_ want to
model the entire processor in VHDL, because I want to be able to change
the processor's specifications in the code, including those of the cache.

If anyone has encountered similar problems (I'd be surprised if I were
the first!), please tell me how you solved them.

Thanks in advance,

Marnix.
--

I  Faculty of Electrical Engineering,  Delft University of Technology        I
I  "Engineering is the art of moulding materials we do not fully             I
I   understand into shapes we cannot fully analyse and preventing            I
I   the public from realising the full extent of our ignorance."             I



Sun, 12 Oct 1997 03:00:00 GMT  
 Synthesizing RAM bank from VHDL?

Quote:

>Hello everybody,

>I'm currently writing a VHDL description of a Cache RAM. I intend to use it
>as part of a microprocessor description, which I want to synthesize using
>the Synopsys Design Compiler.

>My problem is the following:
>How can I tell Synopsys in VHDL to make a RAM bank (size about 30 kbyte,
>should be variable) without having it try to optimize it (that would cost
>far too much time, and would seem a bit pointless to me, RAM having such
>a regular structure). I noticed the Designware RAMS shouldn't be bigger
>than 256 bits, for just that reason (excessive compile times).

>It says in the Designware components databook:
>"If a large memory is required, use a
>RAM hard macro if it is available in the ASIC library you are
>using and use one of the DW03 FIFO controllers."

>Sure, but can I use such a 'RAM hard macro' (whatever that is, probably
>technology dependent) in my VHDL description? And yes, I _do_ want to
>model the entire processor in VHDL, because I want to be able to change
>the processor's specifications in the code, including those of the cache.

>If anyone has encountered similar problems (I'd be surprised if I were
>the first!), please tell me how you solved them.

>Thanks in advance,

>Marnix.

We usually do not synthesize the ram and use a hard macro as you stated above.
For VHDL modelling, we have a behavi{*filter*}model of the ram that contains the
memory array but we do not synthesize this entity/architecture. By never
reading the VHDL code the Synopsys synthesis tool will leave this as a black
box. ie; when you write out the gate level VHDL there will be a component
declaration but not a entity/architecture for the ram. We then use the same
behavi{*filter*}model for the ram as when we were doing RTL sims. When we hand off
the gate level netlist the ASIC vendor will then plug in the hard macro for
the memory. Also, most ASIC vendors have programs that will generate a model
VHDL/Verilog for whatever size memory you want on your device, or we write
our own.

Hope this helps,
Ken Cyr

(Speaking for me not TI)

.



Sun, 12 Oct 1997 03:00:00 GMT  
 Synthesizing RAM bank from VHDL?
|> I'm currently writing a VHDL description of a Cache RAM. I intend to use it
|> as part of a microprocessor description, which I want to synthesize using
|> the Synopsys Design Compiler.
|>
|> My problem is the following:
|> How can I tell Synopsys in VHDL to make a RAM bank (size about 30 kbyte,
|> should be variable) without having it try to optimize it (that would cost

You would not want to synthesise anything but a very small RAM into flip-flops.
30 kbyte => 240 kbit => 240 kFFs => 1200+ kGates. Not to mention the swap
space and CPU years you would need for the synthesis :)

|> Sure, but can I use such a 'RAM hard macro' (whatever that is, probably
|> technology dependent) in my VHDL description? And yes, I _do_ want to
|> model the entire processor in VHDL, because I want to be able to change
|> the processor's specifications in the code, including those of the cache.

Just model the RAM, do not synthesize it. If you actually  will manufacture
the chip sometimes in the future, connect a RAM module on the schematics or
on the layout, or investigate whether you can use DesignWare macros. On-chip
RAMs are always specific to each vendor - do not expect technology independence.

--


ESA/ESTEC WS
European Space Agency                          Phone: +31-71-65 33 67
European Space Research & Technology Centre    Fax:   +31-71-65 42 95



Mon, 13 Oct 1997 03:00:00 GMT  
 Synthesizing RAM bank from VHDL?

Quote:

>Hello everybody,

>I'm currently writing a VHDL description of a Cache RAM. I intend to use it
>as part of a microprocessor description, which I want to synthesize using
>the Synopsys Design Compiler.

>My problem is the following:
>How can I tell Synopsys in VHDL to make a RAM bank (size about 30 kbyte,
>should be variable) without having it try to optimize it (that would cost
>far too much time, and would seem a bit pointless to me, RAM having such
>a regular structure). I noticed the Designware RAMS shouldn't be bigger
>than 256 bits, for just that reason (excessive compile times).

The solution is to build a behavi{*filter*}model of the RAM for simulation
then use a RAM standard cell from your vendor library.  You can avoid
technology/vendor dependence by making a general purpose RAM and then
using the configuration statement to map it to the specific RAM block
from the vendor of your device.

entity RAM is generic (
    address_msb: natural := 10;
    data_msb:    natural := 31)
port (
    address:   in    std_ulogic_vector(address_msb downto 0);
    data_i:    in    std_ulogic_vector(data_msb downto 0);
    data_o:    out   std_ulogic_vector(data_msb downto 0);
    read:      in    std_ulogic;
    write:     in    std_ulogic);
end RAM;

ram_1:  ram generic map (14, 39)      --  This instantiates a 32K by 40 bit RAM
    port map ( ....)

Do not expect Synopsys (or other synthesis tools) to generate
large RAM's from gates.  You need to use the vendor RAM blocks
or use a specific RAM generator such as Sagantec.


SHELOR ENGINEERING                     VHDL Training, Consulting, Models
3308 Hollow Creek Rd                   (817) 467-9367
Arlington,  TX  76017-5346



Wed, 15 Oct 1997 03:00:00 GMT  
 
 [ 4 post ] 

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