How to use macro in VHDL? 
Author Message
 How to use macro in VHDL?

    Hi! I an a VHDL user.  Recently I found there is a package in
  synopsys lnc. system called IEEE_asic. In this package, there are
  two source code -- BM_std_logic.vhd and SM_std_logic.vhd --. In
  SM_std_logic.vhd, there contains the macro such as AND2MAC, DFFMAC....
  If anyone had used such macro, could you tell me how to include such
  macro and how to use it. If possible, it is better to give me some
  examples.  Thanks.

                      Stockwood in NCTU.TW



Sun, 18 Feb 1996 11:14:59 GMT  
 
 [ 1 post ] 

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