"bad synchronous description" in Xilinx WebPack 
Author Message
 "bad synchronous description" in Xilinx WebPack

Hello
I get this error message in Xilinx WebPack 5.1i that I do not
understand:
"Signal irq_register<6> cannot be synthesized, bad synchronous
description"

-------------------------------------------------------------
   Write_IRQ_register : process (Reset_IRQ_register, GPA, Clock_wr,
                    IOWR,GPCS1, Reset_done, Set_IRQ_register) begin

      if (Reset_done(1)='0') then
         IRQ_register <="00000000";
         Reset_done(1) <= '1';

      elsif (GPA = Adr_IRQ_register and Clock_wr'event and
            Clock_wr ='0' and  IOWR ='0' and GPCS1 = '0') then
         IRQ_register(7) <= GPD_in(7);

      elsif (Reset_IRQ_register ='1') then  
         IRQ_register(2 downto 0) <= "000";

      else
         IRQ_register(2 downto 0) <= Set_IRQ_register(2 downto 0)
                                       or IRQ_register(2 downto 0);    
         IRQ_register(6 downto 3) <= Set_IRQ_register(6 downto 3);
      end if;  

   end Process;
--------------------------------------------------------

I have checked that no other processes are writing to irq_register.
Any help is appreciated.
Thank you in advance.

Nick Hansen



Tue, 26 Apr 2005 20:48:17 GMT  
 "bad synchronous description" in Xilinx WebPack
Nick,

You do indeed have a "bad synchronous description". You have a mix of
synchronous and sequential statements in your process. Your process reads
like a sequential process (no clock) but it has a "clock'event" in it. So it
is neither a pure sequential process nor a pure synchronous process.

The clock-event clause can only contain the clock-event by itself for proper
synthesis using the Xilinx toolset.

Bad Example: (similar to your code)...
...
if reset = '0' then
...
elsif a=b and c=d and falling_edge(clock) then
...

This won't synthesize. The synthesis toolset won't be able to handle it,
even though it looks good logically. The a=b and c=d conditionals must be
placed after the clock event test in their own "if" section. Synthesis tools
in general won't allow conditionals on a clock event. A clock is a clock, a
somewhat special signal, and not a logic signal per-se as far as most
synthesizers are concerned.

You normally want just two tests in your process: reset and your clock
event. This is over simplifying, but probably 95% of all synchronous
processes I've seen are built this way.

Write your process this way:
...
if reset = '0' then
...
elsif falling_edge (clock) then
    if a=b and c=d then ...
    ...
    end if;
end if;

(Note the subordinated "if" structure. The rest of your code goes under this
second-level "if" )

Also, note that "falling_edge(clock)" is a std macro for " if clock'event
and clock = '0'" and is easier to read.

Further, you do not need to include other signal names in the sensitivity
list in a
synchronous process...just the signals that you have in your outermost
"if...elsif...elsif...end if;" code, such as just the "clock", "reset"
and/or "set" signals.


Quote:
> Hello
> I get this error message in Xilinx WebPack 5.1i that I do not
> understand:
> "Signal irq_register<6> cannot be synthesized, bad synchronous
> description"

> -------------------------------------------------------------
>    Write_IRQ_register : process (Reset_IRQ_register, GPA, Clock_wr,
>                     IOWR,GPCS1, Reset_done, Set_IRQ_register) begin

>       if (Reset_done(1)='0') then
>          IRQ_register <="00000000";
>          Reset_done(1) <= '1';

>       elsif (GPA = Adr_IRQ_register and Clock_wr'event and
>             Clock_wr ='0' and  IOWR ='0' and GPCS1 = '0') then
>          IRQ_register(7) <= GPD_in(7);

>       elsif (Reset_IRQ_register ='1') then
>          IRQ_register(2 downto 0) <= "000";

>       else
>          IRQ_register(2 downto 0) <= Set_IRQ_register(2 downto 0)
>                                        or IRQ_register(2 downto 0);
>          IRQ_register(6 downto 3) <= Set_IRQ_register(6 downto 3);
>       end if;

>    end Process;
> --------------------------------------------------------

> I have checked that no other processes are writing to irq_register.
> Any help is appreciated.
> Thank you in advance.

> Nick Hansen



Wed, 27 Apr 2005 00:43:18 GMT  
 
 [ 2 post ] 

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