Integrating a Clock into code 
Author Message
 Integrating a Clock into code

I'm pretty new to VHDL and am having problems getting my code to sync
up with a clock.  I have the wait statement in a process, but the
external port mappings seem to execute no matter what I set the clock
to.  I figure it's a simple syntatical fix...
Thanks,
Scott

-------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_components.all;
use WORK.all;

entity alu_unit is
        generic (
                        alu_width                       : NATURAL :=
4;
                        alu_op_width            : NATURAL := 3
        );
        port (
                CLK                                             : in
STD_LOGIC;
                alu_op                                  : in
STD_LOGIC_VECTOR (alu_op_width-1 downto 0);
                alu_a, alu_b                    : in STD_LOGIC_VECTOR
(alu_width-1 downto 0);
                alu_zero, alu_co                : out STD_LOGIC;
                alu_sum                                 : out
STD_LOGIC_VECTOR (alu_width-1 downto 0);
                alu_overflow                    : out STD_LOGIC
        );
end alu_unit;

architecture structure of alu_unit is

        component alu_decoder
                generic (
                        adec_width                      : NATURAL :=
4;
                        adec_op_width           : NATURAL := 3
                );
                port (
                        adec_ALUOP                      : in
std_logic_vector(adec_op_width-1 downto 0);
                        adec_A                          : in
std_logic_vector(adec_width-1 downto 0);
                        adec_B                          : in
std_logic_vector(adec_width-1 downto 0);
                        adec_OUT_A                      : out
std_logic_vector(adec_width-1 downto 0);
                        adec_OUT_B                      : out
std_logic_vector(adec_width-1 downto 0);
                        adec_OUT_CI             : out std_logic
                );
        end component;

        component adder
                generic (
                        add_width               : NATURAL := 4
                );
                port (
                        add_A                   : in
std_logic_vector(add_width-1 downto 0);
                        add_B                   : in
std_logic_vector(add_width-1 downto 0);
                        add_CI                  : in std_logic :='0';
                        add_SUM                 : out
std_logic_vector(add_width-1 downto 0);
                        add_CO                  : out std_logic
                );
        end component;

        component alu_evaluator
                generic (
                        eval_width                      : NATURAL := 4
                );
                port (
                        eval_A                          : in
std_logic_vector(eval_width-1 downto 0);
                        eval_B                          : in
std_logic_vector(eval_width-1 downto 0);
                        eval_SUM                        : in
std_logic_vector(eval_width-1 downto 0);
                        eval_OP                         : in
std_logic;  --indicates add (0), sub (1)
                        eval_overflow           : out std_logic;
                        eval_zero                       : out
std_logic
                );
        end component;

        signal sig_a, sig_b             : std_logic_vector(alu_width-1
downto 0);
        signal sig_carry                : std_logic;
        signal sig_sum                  : std_logic_vector(alu_width-1
downto 0);
begin
        process
        begin
                wait until (CLK'event and CLK = '1');
        end process;
        DECODER1 : alu_decoder
                generic map (alu_width,alu_op_width)
                port map (alu_op, alu_a, alu_b, sig_a, sig_b,
sig_carry);
        ADD1 : adder
                generic map (alu_width)
                port map (sig_a, sig_b, sig_carry ,sig_sum,alu_co);
        EVAL1 : alu_evaluator
                generic map (alu_width)
                port map (alu_a, alu_b, sig_sum,
alu_op(alu_op_width-1), alu_overflow, alu_zero);
        --write out the sum
        alu_sum <= sig_sum;
end structure;

configuration CFG_alu_unit of alu_unit is
        for structure
                for DECODER1 : alu_decoder
                        use configuration WORK.CFG_alu_decoder;
                end for;
                for ADD1 : adder
                        use configuration WORK.CFG_adder;
                end for;
                for EVAL1 : alu_evaluator
                        use configuration WORK.CFG_alu_evaluator;
                end for;
        end for;
end CFG_alu_unit;



Sat, 18 May 2002 03:00:00 GMT  
 Integrating a Clock into code

Quote:

> I'm pretty new to VHDL and am having problems getting my code to sync
> up with a clock.  I have the wait statement in a process, but the
> external port mappings seem to execute no matter what I set the clock
> to.  I figure it's a simple syntatical fix...
> Thanks,
> Scott

since your components alu_decoder,adder and alu_evaluator have no
clocks, i assume that they are combinatorial logic. and i think what you
want is an registered output of your alu like this

                +-----+              +----------+
                |     |              |          |        
     inputs  ---> ALU --- Outputs ---> Register --- clocked Outputs -->
                |     |       Clock-->          |
                +-----+              +----------+

to create this you hate to assign all the output signals of your adder
in the clocked process. the clocked process you are using now is quite
useless. since no actions or assignments are in it. if you want to have
the output registered (sig_sum) then place the assignment
"alu_sum<=sig_sum" in the clocked process. this will cause alu_sum
updated at the rising edge only --> the behavior of a register.

        process
        begin
                 wait until (CLK'event and CLK = '1');

                alu_sum<=sig_sum;
        end process;

Bye, Kai

By the way, how is the weather in hawaii ?
--
------------------------------------------
Dipl. Ing. Kai Troester

IMMS - Institut fuer Mikroelektronik-
und Mechatronik-Systeme gGmbH

Langewiesener Strasse 22
98693 Ilmenau
Germany
Tel:    +49(3677)6783-42
Fax:    +49(3677)6783-38

-------------------------------------------



Sat, 18 May 2002 03:00:00 GMT  
 Integrating a Clock into code
Thanks for the help.  I'm actually not in Hawai (unfortunately).  But
Southern California is pretty nice this time of year!
Thanks again!
Scott



Quote:

>> I'm pretty new to VHDL and am having problems getting my code to sync
>> up with a clock.  I have the wait statement in a process, but the
>> external port mappings seem to execute no matter what I set the clock
>> to.  I figure it's a simple syntatical fix...
>> Thanks,
>> Scott

>since your components alu_decoder,adder and alu_evaluator have no
>clocks, i assume that they are combinatorial logic. and i think what you
>want is an registered output of your alu like this

>                +-----+              +----------+
>                |     |              |          |        
>     inputs  ---> ALU --- Outputs ---> Register --- clocked Outputs -->
>                |     |       Clock-->          |
>                +-----+              +----------+

>to create this you hate to assign all the output signals of your adder
>in the clocked process. the clocked process you are using now is quite
>useless. since no actions or assignments are in it. if you want to have
>the output registered (sig_sum) then place the assignment
>"alu_sum<=sig_sum" in the clocked process. this will cause alu_sum
>updated at the rising edge only --> the behavior of a register.

>        process
>        begin
>                 wait until (CLK'event and CLK = '1');

>            alu_sum<=sig_sum;
>        end process;

>Bye, Kai

>By the way, how is the weather in hawaii ?
>--
>------------------------------------------
>Dipl. Ing. Kai Troester

>IMMS - Institut fuer Mikroelektronik-
>und Mechatronik-Systeme gGmbH

>Langewiesener Strasse 22
>98693 Ilmenau
>Germany
>Tel:    +49(3677)6783-42
>Fax:    +49(3677)6783-38

>-------------------------------------------



Sat, 18 May 2002 03:00:00 GMT  
 
 [ 3 post ] 

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