help for synthesis 
Author Message
 help for synthesis

Hi,
I do need help. I believe that naming signals as A,B,C (and don't take
care
about how long the vector is (let's synopsys do the work)) makes a
design more
readable than doing it the handcoding-style i.e "00", "01".
For example the following sequence is part of my working library:

LIBRARY ieee;
  USE ieee.std_logic_1164.all;

PACKAGE typetest IS
  TYPE t_mux IS (A, B, C);
END typetest;

PACKAGE BODY typetest IS
END typetest;

Only the type t_mux is defined. And now there is the design which
troubles me:

LIBRARY ieee;
  USE ieee.std_logic_1164.all;
  USE work.typetest.all;

ENTITY ttest IS
  PORT (
         x1,x2  : IN  std_logic_vector (1 downto 0);
         y1 : OUT std_logic_vector(1 downto 0);
         y2 : OUT t_mux
       );
END ttest;

ARCHITECTURE behavior OF ttest IS
BEGIN

P1 : PROCESS(x1)
     BEGIN
       CASE x1 IS
         WHEN "00"   => y1 <= "00";
         WHEN "01"   => y1 <= "01";
         WHEN "10"   => y1 <= "10";
         WHEN others => y1 <= "--";
       END CASE;
     END PROCESS P1;

P2 : PROCESS(x2)
     BEGIN
       CASE x2 is
         WHEN "00"   => y2 <= A;
         WHEN "01"   => y2 <= B;
         WHEN "10"   => y2 <= C;
         WHEN others => null;
       END CASE;
     END PROCESS P2;

END behavior;

Of course no magic. Process P1 will be synthesised as a feed trough,
but look what happens to P2!
I think that 'WHEN others => null;' forces synopsys to build the
coding-logic,
but what CAN I write to get the same bevavior of P1 and P2?

Please post your ideas or mail me
 thanks Hagen

--
====================================================================
University of Rostock                        Tel.: (+49 381) 4983534

www:   http://www.*-*-*.com/ ~ploog/ploog.htm



Sat, 06 Feb 1999 03:00:00 GMT  
 help for synthesis

Hi Hagen,

Quote:

>P2 : PROCESS(x2)
>     BEGIN
>       CASE x2 is
>         WHEN "00"   => y2 <= A;
>         WHEN "01"   => y2 <= B;
>         WHEN "10"   => y2 <= C;
>         WHEN others => null;
>       END CASE;
>     END PROCESS P2;
>END behavior;
>Of course no magic. Process P1 will be synthesised as a feed trough,
>but look what happens to P2!
>I think that 'WHEN others => null;' forces synopsys to build the
>coding-logic,
>but what CAN I write to get the same bevavior of P1 and P2?

The 'WHEN others => null;' statement will force process P2 to keep the
old value of y2 in case x2="11". (You don't assign a new value in that
case.)

Unfortunately the "-" is not a VHDL language element (I wish it was)
but an element of the std_logic/std_ulogic type. Otherwise you could
just write 'WHEN others => y2 <= "-";' or something like this.

Many synthesis tools don't know what to do with the "don't care"
element, though. They just substitute a zero vector
e.g.: 'y1 <= "00";'. So if you are lucky you might get the same result
in process 2 by using 'WHEN others => y2 <= A;'.

-Stefan



Sat, 06 Feb 1999 03:00:00 GMT  
 help for synthesis

Quote:

> Hi,
> I do need help. I believe that naming signals as A,B,C (and don't take
> care
> about how long the vector is (let's synopsys do the work)) makes a
> design more
> readable than doing it the handcoding-style i.e "00", "01".
> For example the following sequence is part of my working library:

> PACKAGE typetest IS
>   TYPE t_mux IS (A, B, C);
> END typetest;
> Only the type t_mux is defined. And now there is the design which
> troubles me:
> P2 : PROCESS(x2)
>      BEGIN
>        CASE x2 is
>          WHEN "00"   => y2 <= A;
>          WHEN "01"   => y2 <= B;
>          WHEN "10"   => y2 <= C;
>          WHEN others => null;
>        END CASE;
>      END PROCESS P2;
> I think that 'WHEN others => null;' forces synopsys to build the
> coding-logic,

Hagen, Try fixing your code like
below.

  PACKAGE typetest IS
    TYPE t_mux IS (A, B, C,
dontcare); -- Don't care state
"dontcare" added
    attribute ENUM_ENCODING :
STRING;
    attribute ENUM_ENCODING of
t_mux : type is "00 01 10 DD";
    --
assign DD to "dontcare"  ^^
    --  Let A, B and C be 00, 01
and 10, respectively, as same as
the default
  END typetest;

  -- Lines omitted ...

  P2 : PROCESS(x2)
       BEGIN
         CASE x2 is
           WHEN "00"   => y2 <= A;
           WHEN "01"   => y2 <= B;
           WHEN "10"   => y2 <= C;
           WHEN others => y2 <=
dontcare;
           -- y2 must be assigned
in all processing paths
         END CASE;
       END PROCESS P2;

Synopsys does not automatically
determine the bit-patterns for
enumaration
type which includes "Don't care"
state. You must tell Synopsys tool
which value is "Don't care" state
if you want to use "Don't care"
assignment.

Hope this helps.

Kenji Iwamura



Sun, 07 Feb 1999 03:00:00 GMT  
 help for synthesis

Quote:

> Hagen, Try fixing your code like
> below.

>   PACKAGE typetest IS
>     TYPE t_mux IS (A, B, C,
> dontcare); -- Don't care state
> "dontcare" added
>     attribute ENUM_ENCODING :
> STRING;
>     attribute ENUM_ENCODING of
> t_mux : type is "00 01 10 DD";
>     --
> assign DD to "dontcare"  ^^
>     --  Let A, B and C be 00, 01
> and 10, respectively, as same as
> the default
>   END typetest;

>   -- Lines omitted ...

>   P2 : PROCESS(x2)
>        BEGIN
>          CASE x2 is
>            WHEN "00"   => y2 <= A;
>            WHEN "01"   => y2 <= B;
>            WHEN "10"   => y2 <= C;
>            WHEN others => y2 <=
> dontcare;
>            -- y2 must be assigned
> in all processing paths
>          END CASE;
>        END PROCESS P2;

> Synopsys does not automatically
> determine the bit-patterns for
> enumaration
> type which includes "Don't care"
> state. You must tell Synopsys tool
> which value is "Don't care" state
> if you want to use "Don't care"
> assignment.

> Hope this helps.

> Kenji Iwamura


  YAEH! YIP! IT DOES!
  HAGEN
--
====================================================================
University of Rostock                        Tel.: (+49 381) 4983534

www:   http://www-md.e-technik.uni-rostock.de/~ploog/ploog.htm


Sun, 07 Feb 1999 03:00:00 GMT  
 
 [ 4 post ] 

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