Std_logic_vector generic width question. 
Author Message
 Std_logic_vector generic width question.

Hi,
I have an entity where one input is declared using a generic as follow:

Input    : IN STD_LOGIC_VECTOR((width-1) downto 0);

I'd like to check if this signal is equal to 0, is there a syntax that would
allow me to do it without knowing the value of 'width'? I want to avoid
writing this...

IF Input = "0000" THEN

...since I need to manually change the lenght of the zero vector everytime I
change the value of width.

Thanks
David



Tue, 06 Sep 2005 14:49:05 GMT  
 Std_logic_vector generic width question.

Quote:
> Input    : IN STD_LOGIC_VECTOR((width-1) downto 0);

> I'd like to check if this signal is equal to 0, is there a syntax that
> would allow me to do it without knowing the value of 'width'?

Most compilres should be able to handle a compare against 0 these days, but
if yours does not: define a constant of the same type (width-1 DOWNTO 0),
and make it 0 with (OTHERS => '0'). Compare against that constant.

Regards,

Pieter Hulshoff



Tue, 06 Sep 2005 15:27:44 GMT  
 Std_logic_vector generic width question.
Hi David,

probably a conversion from std_logic_vector to integer could to the
trick. Convert the std_logic_vector with one of the already available
functions (I think it's to_integer(
and then check for a Zero.
....
  Input    : IN STD_LOGIC_VECTOR((width-1) downto 0):=(others=>'0');
  dummy: integer:=0;
....
dummy<=to_integer(input, width-1);
if dummy=1 then
...

Possibly you have to run two conversions to get from std_logic to
integer but check the source-code for the IEEE-libraries (e.g. in the
Modelsim installation).

Cheers,

Martin

Quote:

> Hi,
> I have an entity where one input is declared using a generic as follow:

> Input    : IN STD_LOGIC_VECTOR((width-1) downto 0);

> I'd like to check if this signal is equal to 0, is there a syntax that would
> allow me to do it without knowing the value of 'width'? I want to avoid
> writing this...

> IF Input = "0000" THEN

> ...since I need to manually change the lenght of the zero vector everytime I
> change the value of width.

> Thanks
> David



Tue, 06 Sep 2005 15:13:02 GMT  
 Std_logic_vector generic width question.
Hi David,
       Use attributes, in your case you could do:

if  (inp_vec = (inp_vec'range => '0')) then
..
end if

Also see FAQ http://www.vhdl.org/comp.lang.vhdl/FAQ1.html#const_vectors

HTH,
Srinivasan


Quote:
> Hi,
> I have an entity where one input is declared using a generic as follow:

> Input    : IN STD_LOGIC_VECTOR((width-1) downto 0);

> I'd like to check if this signal is equal to 0, is there a syntax that
would
> allow me to do it without knowing the value of 'width'? I want to avoid
> writing this...

> IF Input = "0000" THEN

> ...since I need to manually change the lenght of the zero vector everytime
I
> change the value of width.

> Thanks
> David

> --

Srinivasan Venkataramanan
Senior Verification Engineer
Software & Silicon Systems India Pvt Ltd. - an Intel company
Bangalore, India

http://www.noveldv.com

I don't speak for Intel



Tue, 06 Sep 2005 15:42:00 GMT  
 Std_logic_vector generic width question.
Hi,

Quote:
> Most compilres should be able to handle a compare against 0 these days,
but
> if yours does not: define a constant of the same type (width-1 DOWNTO 0),

How would you write this 'compare against 0'? I'm using Xilinx ISE and
modelsim. I suppose they should support this.
Thanks
David


Quote:
> > Input    : IN STD_LOGIC_VECTOR((width-1) downto 0);

> > I'd like to check if this signal is equal to 0, is there a syntax that
> > would allow me to do it without knowing the value of 'width'?

> Most compilres should be able to handle a compare against 0 these days,
but
> if yours does not: define a constant of the same type (width-1 DOWNTO 0),
> and make it 0 with (OTHERS => '0'). Compare against that constant.

> Regards,

> Pieter Hulshoff



Tue, 06 Sep 2005 16:04:53 GMT  
 Std_logic_vector generic width question.

Quote:
> How would you write this 'compare against 0'? I'm using Xilinx ISE and
> modelsim. I suppose they should support this.

IF input = 0 THEN

It might be that numeric_std or std_logic_arith is needed for this
comparison, but I currently don't have the tools to check. Comparing
vectors to integers is supported in one of those libraries
(std_logic_vector, numeric_std or std_logic_arith) as far as I remember.

Regards,

Pieter Hulshoff



Tue, 06 Sep 2005 16:25:04 GMT  
 Std_logic_vector generic width question.

Quote:
> > Input    : IN STD_LOGIC_VECTOR((width-1) downto 0);
> > I'd like to check if this signal is equal to 0>
> Most compilres should be able to handle a compare against 0 these days

NOOOOO!  PLEASE don't start erroneous myths like this!
It is NOTHING to do with what "compilers can handle", and
EVERYTHING to do with how the language deals with operations
on user-defined types (note that STD_LOGIC_VECTOR is effectively
a user-defined type - it's not part of the core language).

If your compiler allows you to compare a std_logic_vector
with an integer, *without* using a suitable package, then
your compiler is wrong, broken, non-conforming, trash.

The core language ABSOLUTELY DOES NOT permit the comparison of
a std_logic with an integer, because they are of different types.
The comparison operators (=, > etc) automatically work in a
sensible way between two operands of the same vector type,
but if you want to be able to compare two operands of DIFFERENT
type you must create your own overloaded version of the comparison
operator.

The std_logic_unsigned package does precisely this, and therefore
allows you to write the comparison

  Input = 0

But std_logic_unsigned is so very horrible in so many ways that
there is really no excuse for using it.  Instead, use
numeric_std (or std_logic_arith if you have some historical
reason for so doing).  This package defines new types
UNSIGNED and SIGNED with exactly the same definitions as
STD_LOGIC_VECTOR, and...

Oh, I hear the sound of yawning in the back row.  OK
then, I'll shut up and just tell you to read the FAQ.

By the way, the original poster asked...

Quote:
> > is there a syntax that
> > would allow me to do it without knowing the value of 'width'?

Use
  input = (others => '0')
as several other people have suggested.
--
Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * Perl * Tcl/Tk * Verification * Project Services

Doulos Ltd. Church Hatch, 22 Market Place, Ringwood, Hampshire, BH24 1AW, UK

Fax: +44 (0)1425 471573                           Web: http://www.doulos.com

The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.



Tue, 06 Sep 2005 16:44:55 GMT  
 Std_logic_vector generic width question.

Quote:
> NOOOOO!  PLEASE don't start erroneous myths like this!
> It is NOTHING to do with what "compilers can handle", and
> EVERYTHING to do with how the language deals with operations
> on user-defined types (note that STD_LOGIC_VECTOR is effectively
> a user-defined type - it's not part of the core language).

Yes, I know it's supposed to be handled by one of the libraries (numeric_std
or std_logic_arith). I also know that there are some faulty library
implementations out there (several compilers use internal libraries for
these purposes) that cause faulty behaviour. Hence it is dependent on your
compiler as well. I agree though that I should have been more clear from
the start. My apologies for this.

Quote:
> Use
>   input = (others => '0')
> as several other people have suggested.

Actually, I'm not sure if this statement will work. Comparing against a
constant of that value should, but I remember some interesting behaviour
from statements like this one in the past.

Regards,

Pieter Hulshoff



Tue, 06 Sep 2005 17:04:43 GMT  
 Std_logic_vector generic width question.
On Fri, 21 Mar 2003 10:04:43 +0100, Pieter Hulshoff

Quote:

>> NOOOOO!  PLEASE don't start erroneous myths like this!
>> It is NOTHING to do with what "compilers can handle", and
>> EVERYTHING to do with how the language deals with operations
>> on user-defined types (note that STD_LOGIC_VECTOR is effectively
>> a user-defined type - it's not part of the core language).

>Yes, I know it's supposed to be handled by one of the libraries (numeric_std
>or std_logic_arith). I also know that there are some faulty library
>implementations out there (several compilers use internal libraries for
>these purposes) that cause faulty behaviour. Hence it is dependent on your
>compiler as well. I agree though that I should have been more clear from
>the start. My apologies for this.

>> Use
>>   input = (others => '0')
>> as several other people have suggested.

>Actually, I'm not sure if this statement will work. Comparing against a
>constant of that value should, but I remember some interesting behaviour
>from statements like this one in the past.

input = (input'range => '0')

works a lot better.

Regards,
Allan.



Tue, 06 Sep 2005 17:18:21 GMT  
 Std_logic_vector generic width question.

Quote:
> input = (input'range => '0')
> works a lot better.

Indeed! :)

Regards,

Pieter Hulshoff



Tue, 06 Sep 2005 17:20:16 GMT  
 Std_logic_vector generic width question.
Hi,


<SNIP>

Quote:
> By the way, the original poster asked...

> > > is there a syntax that
> > > would allow me to do it without knowing the value of 'width'?

> Use
>   input = (others => '0')
> as several other people have suggested.

  Unfortunately that won't work. See FAQ
http://www.vhdl.org/comp.lang.vhdl/FAQ1.html#const_vectors

Srini

--
Srinivasan Venkataramanan
Senior Verification Engineer
Software & Silicon Systems India Pvt Ltd. - an Intel company
Bangalore, India

http://www.noveldv.com

I don't speak for Intel



Tue, 06 Sep 2005 18:47:38 GMT  
 Std_logic_vector generic width question.

Quote:
> > Use
> >   input = (others => '0')
> > as several other people have suggested.

>   Unfortunately that won't work. See FAQ
> http://www.vhdl.org/comp.lang.vhdl/FAQ1.html#const_vectors

Yes, that was an embarrassing slip.  Sorry.

Allan Herriman posted one of several possible fixes.
I usually try to declare subtypes for everything that
matters to me, and then I can do things like this:

  subtype WORD is std_logic_vector(word_length-1 downto 0);
  ...
    if MyWord = WORD'(others => '0') then ...
--
Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * Perl * Tcl/Tk * Verification * Project Services

Doulos Ltd. Church Hatch, 22 Market Place, Ringwood, Hampshire, BH24 1AW, UK

Fax: +44 (0)1425 471573                           Web: http://www.doulos.com

The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.



Tue, 06 Sep 2005 22:16:11 GMT  
 
 [ 12 post ] 

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