Logic Cells 
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 Logic Cells

Hi I was wondering how exactly vhdl code is converted and how the compiler
decides the number of logic cells that are needed to run the code.
Basically my question is, what kind of things should I avoid to keep the
number of logic cells to a minimum.  Thanks.

-Luis



Thu, 30 Jan 2003 03:00:00 GMT  
 Logic Cells

Quote:

> Hi I was wondering how exactly vhdl code is converted and how the compiler
> decides the number of logic cells that are needed to run the code.
> Basically my question is, what kind of things should I avoid to keep the
> number of logic cells to a minimum.  Thanks.

That is a very general question. The number of logic cells used depends
on what you are designing in such a complex way that it is hard to
describe how to minimize the count. I can relate my experience on a
project where I used VHDL.

I started out using a very bad tool, OrCAD Express. I did not intend to
do my work in VHDL, but they taught it as part of the training class and
I liked the advantages. So I started coding my work in VHDL only to find
that the compiler was very erratic and crashed a lot. One of the things
I had trouble with was trying to get the compiler to generate the logic
that I wanted. For example, the use of the clock enables was essential
to getting a fast design. The compiler had a lot of difficulty using the
CE inputs on the Xilinx FFs. Did I mention that the compiler crashed a
lot?

So with about 25% of my work coded and tested, I switched to the Xilinx
Foundation tools. I found many of the techniques used to get the logic I
wanted from the OrCAD compiler did not work well with the Model Tech
compiler from Xilinx. This was rather distressful since the method I
used to figure this out took a lot of time. I would try some code and
compile it. Then I would examine the EDIF file to see what logic was
produced. This was not exactly a lot of fun. I eventually learned to
first focus on the FMAPS that were used to control the logic mapping.
This would expedite things in some cases.

So once I learned how to produce efficient code for the Model Tech
compiler, Xilinx changed the compiler in an update to FPGA Express.
Again, my code was broken in the update so that it produced inefficient
logic again. This time I was about 50% done. But now I knew the routine,
but I found that FPGA Express had a real problem with 'One Hot' encoded
FSMs. That took some work to get around.

In the end, the process of reverse engineering the EDIF (or XNF) files
was the only way I could see what the compiler was doing. Now many of
the tools provide a schematic viewer to do the reverse engineering for
you. But you will need to run this and look carefully at what has been
produced. Of course the most important thing in all this is that you
should have a clear idea of what logic you were trying to describe. Then
the hard part is getting the compiler to give you what you wanted.

Don't treat the compiler as a "black box" that produces magical chip
designs. Know what logic you want and then learn how to make the tools
give it to you. In Xilinx parts it helps if you think in terms of 4
input LUTs. They are the bricks of all logic design and if you aren't
using them efficiently, you will not end up with a good design.

--

Rick Collins


Ignore the reply address. To email me use the above address with the XY
removed.

Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design

Arius
4 King Ave
Frederick, MD 21701-3110
301-682-7772 Voice
301-682-7666 FAX

Internet URL http://www.arius.com



Thu, 30 Jan 2003 03:00:00 GMT  
 Logic Cells
Hi Luis,
have a look at this :

IEEE P1076.6/D1.12
Draft Standard For VHDL Register
Transfer Level Synthesis

This publication describes how sourcecode is converted to logical
elements.
(e.g. Case to MUX etc.)
Of course your tool might slightly differ from the standard (as most
tools do).

Have a nice Synthesis.

   Eilert

Quote:
>>>>>>>>>>>>>>>>>> Ursprngliche Nachricht <<<<<<<<<<<<<<<<<<


Cells:

Quote:
> Hi I was wondering how exactly vhdl code is converted and how the
compiler
> decides the number of logic cells that are needed to run the code.
> Basically my question is, what kind of things should I avoid to keep the
> number of logic cells to a minimum.  Thanks.
> -Luis



Fri, 31 Jan 2003 03:00:00 GMT  
 
 [ 3 post ] 

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