Formal grammar for VHDL 
Author Message
 Formal grammar for VHDL

  I am in the process of writing a VHDL parser in Prolog.
  I need a formal grammar of VHDL written in Prolog (a la DCG)
  Any pointer on this topic is more than welcome.
  Thank you for your help.

Claude Fleurey

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Claude Fleurey
IBM France
Components Development Laboratory
DPT 1045 (Y1M)
224 Bd Kennedy
91105 Corbeil Essonnes CEDEX

Tel  : 33 - 1 - 60 88 56 63
Fax  : 33 - 1 - 60 88 49 20
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Fri, 27 Oct 1995 20:00:18 GMT  
 
 [ 1 post ] 

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