clock skew and clock overloading 
Author Message
 clock skew and clock overloading

Hi everyone,

I am working on a design that has 32 shift registers (10 bits each).
All shift registers will be using the same clocks and I fear that clock
skew and clock overloading will be a problem.

Yesterday, I read in Peter Ashenden's book ,"The Designer's Guide to
VHDL" (page 340-343) about a recursive structure called a "fanout tree"
that may help me.  Here are my questions:

    1. I don't know how to connect the outputs of the fanout tree to the
inividual registers in a way that alleviates the clock skew/clock
overloading problems.

    2.  Has anyone used this structure in a similar circumstance?

    3.  Does anyone have any other ideas regarding clock skew and clock
overloading in the context presented here?

Any and all suggestions are greatly appreciated.  I include my code
below, which must then be used in a generate statement to generate 32 of
these shift registers.

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;

entity first_shift_10 is
        port (coeff_clock,  sample_clock, d_in : in std_logic;
                shift_enable : in std_logic;
                shift_out : out std_logic_vector (9 downto 0) );
end first_shift_10;

architecture behave of first_shift_10 is

        signal shift_reg : std_logic_vector(9 downto 0);
        begin
                shift : process(coeff_clock, shift_enable)
                begin

                        if (coeff_clock'event and coeff_clock='1') then
    if (shift_enable = '1') then
                                shift_reg(9 downto 1) <= shift_reg(8
downto 0);
                                shift_reg(0) <= d_in;
                        end if;
  end if;
                end process shift;

                to_mult : process(sample_clock)
                begin
                        if sample_clock'event and sample_clock='1' then
                                shift_out <= shift_reg;
                        end if;
                end process to_mult;

END behave;

--
Gorge A. Bueso
Lucent Technologies



Sun, 01 Oct 2000 03:00:00 GMT  
 clock skew and clock overloading

I am new to VHDL and I know almost nothing about ASIC design. But in the
Orcad class I just took they indicated that when designing ASIC clocks,
you don't/can't specify the clocking tree in VHDL. That can only be done
in a schematic/custom format for the ASIC.

Of course, this was an entry level course. So the info may not be
reliable. Does anyone with ASIC experience know if this is true?

Rick Collins


remove the XY to email me.

Quote:

> Hi everyone,

> I am working on a design that has 32 shift registers (10 bits each).
> All shift registers will be using the same clocks and I fear that clock
> skew and clock overloading will be a problem.

> Yesterday, I read in Peter Ashenden's book ,"The Designer's Guide to
> VHDL" (page 340-343) about a recursive structure called a "fanout tree"
> that may help me.  Here are my questions:

>     1. I don't know how to connect the outputs of the fanout tree to the
> inividual registers in a way that alleviates the clock skew/clock
> overloading problems.

>     2.  Has anyone used this structure in a similar circumstance?

>     3.  Does anyone have any other ideas regarding clock skew and clock
> overloading in the context presented here?

> Any and all suggestions are greatly appreciated.  I include my code
> below, which must then be used in a generate statement to generate 32 of
> these shift registers.

> library ieee;
> use ieee.std_logic_1164.all;
> use ieee.std_logic_arith.all;

> entity first_shift_10 is
>         port (coeff_clock,  sample_clock, d_in : in std_logic;
>                 shift_enable : in std_logic;
>                 shift_out : out std_logic_vector (9 downto 0) );
> end first_shift_10;

> architecture behave of first_shift_10 is

>         signal shift_reg : std_logic_vector(9 downto 0);
>         begin
>                 shift : process(coeff_clock, shift_enable)
>                 begin

>                         if (coeff_clock'event and coeff_clock='1') then
>     if (shift_enable = '1') then
>                                 shift_reg(9 downto 1) <= shift_reg(8
> downto 0);
>                                 shift_reg(0) <= d_in;
>                         end if;
>   end if;
>                 end process shift;

>                 to_mult : process(sample_clock)
>                 begin
>                         if sample_clock'event and sample_clock='1' then
>                                 shift_out <= shift_reg;
>                         end if;
>                 end process to_mult;

> END behave;

> --
> Gorge A. Bueso
> Lucent Technologies



Sun, 01 Oct 2000 03:00:00 GMT  
 clock skew and clock overloading

I asked the exact same question and I rec'd some fine answers...

1) Make sure you use a low skew clock..this usually is an instantiated
component from the foundry(such as CKTPAD for Quicklogic or Xilinx's
GBuffers) prior to synthesis.
   ...these instantiations will provide a very low skew clock tree. I
don't know of any VHDL code that guarantees the use of a low skew clock
apart from instantianting
foundry specific components dedicated for such a purpose. These foundry
specific instantiations are usually fanout-independent...

2)Of course the obvious: make sure your shift registers are connected
directly to the low skew clock; don't gate this clock...if you require
the clock only for a period of time then use an enable function(just as
you have below) as the gate.

3)If clock skew is still a problem and you have some ff's to spare,
insert ff's in between the other ff's but have these new ff's clocked by
the inverted edge of your serial register. Hence, this will eliminate
skew up to 1/2 a clock cycle.

Quote:

> I am new to VHDL and I know almost nothing about ASIC design. But in the
> Orcad class I just took they indicated that when designing ASIC clocks,
> you don't/can't specify the clocking tree in VHDL. That can only be done
> in a schematic/custom format for the ASIC.

> Of course, this was an entry level course. So the info may not be
> reliable. Does anyone with ASIC experience know if this is true?

> Rick Collins


> remove the XY to email me.


> > Hi everyone,

> > I am working on a design that has 32 shift registers (10 bits each).
> > All shift registers will be using the same clocks and I fear that clock
> > skew and clock overloading will be a problem.

> > Yesterday, I read in Peter Ashenden's book ,"The Designer's Guide to
> > VHDL" (page 340-343) about a recursive structure called a "fanout tree"
> > that may help me.  Here are my questions:

> >     1. I don't know how to connect the outputs of the fanout tree to the
> > inividual registers in a way that alleviates the clock skew/clock
> > overloading problems.

> >     2.  Has anyone used this structure in a similar circumstance?

> >     3.  Does anyone have any other ideas regarding clock skew and clock
> > overloading in the context presented here?

> > Any and all suggestions are greatly appreciated.  I include my code
> > below, which must then be used in a generate statement to generate 32 of
> > these shift registers.

> > library ieee;
> > use ieee.std_logic_1164.all;
> > use ieee.std_logic_arith.all;

> > entity first_shift_10 is
> >         port (coeff_clock,  sample_clock, d_in : in std_logic;
> >                 shift_enable : in std_logic;
> >                 shift_out : out std_logic_vector (9 downto 0) );
> > end first_shift_10;

> > architecture behave of first_shift_10 is

> >         signal shift_reg : std_logic_vector(9 downto 0);
> >         begin
> >                 shift : process(coeff_clock, shift_enable)
> >                 begin

> >                         if (coeff_clock'event and coeff_clock='1') then
> >     if (shift_enable = '1') then
> >                                 shift_reg(9 downto 1) <= shift_reg(8
> > downto 0);
> >                                 shift_reg(0) <= d_in;
> >                         end if;
> >   end if;
> >                 end process shift;

> >                 to_mult : process(sample_clock)
> >                 begin
> >                         if sample_clock'event and sample_clock='1' then
> >                                 shift_out <= shift_reg;
> >                         end if;
> >                 end process to_mult;

> > END behave;

> > --
> > Gorge A. Bueso
> > Lucent Technologies



Mon, 02 Oct 2000 03:00:00 GMT  
 
 [ 4 post ] 

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