HELP:Altera .edo to Vantage Smartmodel 
Author Message
 HELP:Altera .edo to Vantage Smartmodel

I'm having difficulty taking a VHDL design through Altera in order
to get timing information for a back-annotated simulation.
Details: I synthesized the code with exemplar to get a .tdf file for
Altera.  I then targeted a FLEX8000 part with the edif output turned
on.  I then modified the original configuration file I used to do
functional simulation in Vantage to point to the smartmodel with
the .edo (Altera edif output) file for timing.  But I get errors in that
the .edo file contains VDD and GND ports that are not defined in
the smartmodel.
Q: Is there something I can modify in the set-up in Altera to eliminate
these ports? Or are there switches that I need to set and haven't?

Any suggestions would be greatly appreciated.




Fri, 12 Feb 1999 03:00:00 GMT  
 
 [ 1 post ] 

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