xilinx and vhdl... 
Author Message
 xilinx and vhdl...

Hi all,
I have a feeling that Xilinx is favoring Verilog over
VHDL; they offered a verilog tutorial but no vhdl one,
also the latest memory interface core is coded in
verilog....Is this a trend I missed or they are big
enough now to dictate their own preferences and
ignore what I think is a fairly large vhdl user base?
Any illuminating comments are velcome..
jakab


Sun, 27 Jan 2002 03:00:00 GMT  
 
 [ 1 post ] 

 Relevant Pages 

1. Float.p. with Xilinx Express VHDL

2. Xilinx to VHDL translator?

3. Mixed VHDL and Verilog with Xilinx ISE

4. PCB, Cadence, OrCAD, Protel, FPGA, VHDL, Natinst, Xilinx, Siemens Simatic,

5. CAD/CAM/CAE/CFD/PCB-VHDL-FPGA-XILINX/MATH/CHEM/GIS-GPS/from Athens, Greece

6. Verilog model of Xilinx macro in VHDL Testbench fails

7. How get Xilinx VHDL softwaer ?

8. SYNOPSYS, XILINX, VHDL mailing list ?

9. Mixed VHDL and Verilog with Xilinx ISE

10. NEWBIE: xilinx webpack ISE VHDL help!

11. Pad declaration in VHDL module, XILINX ISE4.2

12. Neural Network using VHDL (xilinx)

 

 
Powered by phpBB® Forum Software