designing a Keypad interface logic in VHDL 
Author Message
 designing a Keypad interface logic in VHDL

Hello every one !

Does anybody have any idea that how do design a keypad (keyboard) in
VHDL, the keypad description is as , its a 3 * 3 matrix keypad i-e three
rows and three columns, also there are two signal named  ACK and Key
pressed ( just to acknowledge and sense the key pressed logic ), it
should avoid the key bouncing signals and should not acknowledge when
two keys are pressed at a time.

I am looking forward to hear all of you soon.

Thanks

Rizwan Muhammad



Tue, 20 Mar 2001 03:00:00 GMT  
 designing a Keypad interface logic in VHDL

Quote:

> Hello every one !

> Does anybody have any idea that how do design a keypad (keyboard) in
> VHDL, the keypad description is as , its a 3 * 3 matrix keypad i-e three
> rows and three columns, also there are two signal named  ACK and Key
> pressed ( just to acknowledge and sense the key pressed logic ), it
> should avoid the key bouncing signals and should not acknowledge when
> two keys are pressed at a time.

> I am looking forward to hear all of you soon.

> Thanks

> Rizwan Muhammad

You would design this in VHDL the same way you would design it in any
logic.

I would suggest that you use 2 FFs with three decode outputs to generate
the three output signals. Likewise you will need 3 input signals for the
sense circuit. The sense circuit will stop the output counter and latch
the current state of the input and output for the key pressed value. A
state machine will control all of this circuitry as well as provide a
wait on release of the key for debouncing. Your input sense circuit will
need to perform 2 key detection.

I hope this helps.

--

Rick Collins


remove the XY to email me.



Wed, 21 Mar 2001 03:00:00 GMT  
 
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