Xilinx and std.textio.lib 
Author Message
 Xilinx and std.textio.lib

I'm having trouble using the std.textio.lib in the Xilinx ISE 5.1. I need it
to open a file
for simulating my project. It appears that xilinx doesn't open the library
or simple doesn't
recognize it. It gives me an error in every std.textio command. Does anyone
knows
how to solve this matter?


Fri, 09 Sep 2005 17:57:29 GMT  
 Xilinx and std.textio.lib
Hi John,

as you didn't post any error messages I can only guess.
You are trying to use the textiop in Xilinx so I assume it is used
during synthesis. For that it's not valid.

But as you need it for simulation your design you need it in your
VHDL-code. The way to have it for simulation but nor for synthesis would
be to have all the textio-statements inside
--pragma translate_off
--pragma translate_on
For synthesis the code inside there is invisible, for simulation the
"--pragma" is only a comment and the code inside is used as normal.

As I said, just a guess...

For more info you have to post some more.

Cheers,

Martin

Quote:

> I'm having trouble using the std.textio.lib in the Xilinx ISE 5.1. I need it
> to open a file
> for simulating my project. It appears that xilinx doesn't open the library
> or simple doesn't
> recognize it. It gives me an error in every std.textio command. Does anyone
> knows
> how to solve this matter?



Fri, 09 Sep 2005 21:32:41 GMT  
 Xilinx and std.textio.lib
Hi John,
As the previous reply stated, you can't synthesize any operation that uses
textio. Are you sure
you are not accidently trying to synthesize the Test Bench you are using to
simulate your design.

Best Regards

Andre'

Quote:

> I'm having trouble using the std.textio.lib in the Xilinx ISE 5.1. I need
it
> to open a file
> for simulating my project. It appears that xilinx doesn't open the library
> or simple doesn't
> recognize it. It gives me an error in every std.textio command. Does
anyone
> knows
> how to solve this matter?



Fri, 09 Sep 2005 23:34:44 GMT  
 Xilinx and std.textio.lib
Well, my problem is the following:

I want to test my design with some data from a file. I'm just used to create
testing
waveforms, now the story is different ( it envolves data, times, etc. ). I
thought
i could create a block ( just for simulating purposes ) written in vhdl to
read from the
file and put the data out in several ports. I haven't tried the "--pragma
on" trick yet.
Is there anyother way of doing this?


Quote:
> Hi John,
> As the previous reply stated, you can't synthesize any operation that uses
> textio. Are you sure
> you are not accidently trying to synthesize the Test Bench you are using
to
> simulate your design.

> Best Regards

> Andre'



Quote:
> > I'm having trouble using the std.textio.lib in the Xilinx ISE 5.1. I
need
> it
> > to open a file
> > for simulating my project. It appears that xilinx doesn't open the
library
> > or simple doesn't
> > recognize it. It gives me an error in every std.textio command. Does
> anyone
> > knows
> > how to solve this matter?



Sun, 11 Sep 2005 21:09:35 GMT  
 Xilinx and std.textio.lib

Quote:

> Well, my problem is the following:

> I want to test my design with some data from a file. I'm just used to
create
> testing
> waveforms, now the story is different ( it envolves data, times, etc. ). I
> thought
> i could create a block ( just for simulating purposes ) written in vhdl to
> read from the
> file and put the data out in several ports. I haven't tried the "--pragma
> on" trick yet.
> Is there anyother way of doing this?

  Are you sure you are using the Simulator and NOT Synthesiser to read in
your VHDL TB? As far as I have seen (from Xilinx's tutorials) ISE seems to
support textio for Simulation (See:
http://www.xilinx.com/support/techsup/tutorials/tutorials5.htm)

Srinivasan
--
Srinivasan Venkataramanan
Senior Verification Engineer
Software & Silicon Systems India Pvt Ltd. - an Intel company
Bangalore, India

http://www.noveldv.com http://www.deeps.org

I don't speak for Intel



Sun, 11 Sep 2005 21:36:49 GMT  
 
 [ 5 post ] 

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