synthesize hierarchical VHDL 
Author Message
 synthesize hierarchical VHDL

Hi
I am working on a project where i use hierarchical architecture. I have used
testbenches and simulation models as component at the lowest level (it
seemed natural), but when i tried synthesize the code, the tools are warning
it can't find the components, of course. The question is, if it is possible
to keep in and outs at the lowest level or have i have to move them up to
the highest level port.

Pierre



Tue, 06 Jul 2004 04:58:01 GMT  
 synthesize hierarchical VHDL
Hi

I think you mixed up several questions:

- If your synth tools didn't find the components, make sure the calling code
contains the library containing the component or the component itself.
- If you have an hierarchical design, all in/outs to the outsite world must
be moved to the top. However, you can made one hierarchical level with
multiple components (on that same level). In this senario i/o are not moved.

Kind regards

Johan.


Quote:
> Hi
> I am working on a project where i use hierarchical architecture. I have
used
> testbenches and simulation models as component at the lowest level (it
> seemed natural), but when i tried synthesize the code, the tools are
warning
> it can't find the components, of course. The question is, if it is
possible
> to keep in and outs at the lowest level or have i have to move them up to
> the highest level port.

> Pierre



Sat, 10 Jul 2004 21:58:41 GMT  
 
 [ 2 post ] 

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