FW: Path delay and timer question 
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 FW: Path delay and timer question

I apologize for the re-posting. I am looking to have more inside on my
newcomer questions.

Thanx,
JDS

Quote:

> 1) Depends on whta metric you use.  If average latency is what is
> important, then use the average.  If peak latency is important, you use
> that.  Be aware that average latency may be data dependent, so make sure
> your data set is representative.  In this case, you'll probably need both
> numbers: average to determine the average performance of the system and
> max to make sure the system can handle a worst case scenario.  It may take
> a sizeable effort to determine what a realistic worst case is in the
> context of your system.

I guess that I will require to do create a test harness code to
determine by backannotation, the data dependent performances.
Quote:

> 2) This is usually accomplished with matching delays if the amount of data
> in both paths is similar.  If it is just one or two samples that need to
> be passed around a process thta is producing many samples, then you hold
> it in a register (but that is not the usual case).  The clock frequency
> should match the clock frequency of your process data path, and the
> latency should match the data path latency.  Normally in hardware DSP the
> latency is deterministic, and it is easiest if you try to balance the
> latency through all sub paths so that the outputs come at a fixed time.
> If they are variable or non-deterministic, you should consider putting a
> FIFO in the bypass path.

If I not misunderstood:  Main block has two (2) input paths, #1 the
'process path' which contains a t1 delay processing, and #2 the 'data
path' which has minimum t2 delay. Then I have to  balance those
'data-path' sub paths considering their latencies (assuming register
chained, or FIFO rate matching); and on the 'process path', (assuming
register boundaries delimited) its delay will determine the MAIN clock
frequency. Then, Which kind of FIFO configuration will be the more
appropriate: the I/O only, with limit flags, and/or pointer based? And
How do I determine its depth? Finally, Which is the best way to code
it in  VHDL: using LUTs/RAMs (technology specific) or by a more
general mean (based of F/Fs)?
Quote:

> > Hi everybody,

> > I may have two (2) dummy questions, but I'd like to see how far are my
> > thoughts on that.

> > 1. How do I can measure the performance of DSP block if its processing
> > time varies depending of the data itselft? By instantiation of a known
> > time response circuit in parallel, i.e., a counter with a strobe
> > signal and stop signal coming from the DSP block after it finishes the
> > crunching. Can it be used?

> > 2. Another case: Having two (2) input path to a main logic block; one
> > of them is having a secundary combinational logic; and the secundary
> > path (or input) does not have any logic at all. How do I synchronize
> > the inputs of the main block? Without clock-gating, maybe with many
> > pipeline registers on the empty path. Then, how do I determine the
> > right number of registers and their clock frecuency. What is the right
> > approach?

> > Again, many thanks friends, and Ray thanks to take from your valuable
> > time to allure our lay questions.

> > JDS

> --
> --Ray Andraka, P.E.
> President, the Andraka Consulting Group, Inc.
> 401/884-7930     Fax 401/884-7950

> http://www.*-*-*.com/

>  "They that give up essential liberty to obtain a little
>   temporary safety deserve neither liberty nor safety."
>                                           -Benjamin Franklin, 1759

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Mon, 05 Sep 2005 00:01:21 GMT  
 
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