vhdl, Wait until statement problem in synthesis

#YEO WEE KWONG
#1 / 13

Wait until statement problem in synthesis

Hi,

I wonder why wait until statement when used in a process can generate a
warning of :

Warning: Clock signal is not in the sensitivity list. "pClk"
in routine ntyCounter line 18 in file
'/home/yeowk/vhdl.dir/MyProj.dir/Vhdl.dir/arcCounter.vhd' (HDL-400)

I thought that code (1) is the same as code (2) functionally:

process -- Code(1)
begin
wait until rising_edge(clk);
:
:
:
end process;

process(Clk) - Code(2)
begin
if rising_edge(Clk) then
:
:
:
end if;
end process

I check the Solvit in Synopsys but cannot find any workaround. Can
someone enlightened why the above statement is not accepted in synthesis
engine(particular Synopsys).

By the way, code(2) pass the synthesis without warning! Can you explain?

Yeo Wee Kwong, Sky (Mr)

Sun, 20 Oct 2002 03:00:00 GMT

Andrew MacCormac
#2 / 13

Wait until statement problem in synthesis

Quote:

> Hi,

> I wonder why wait until statement when used in a process can generate a
> warning of :

> Warning: Clock signal is not in the sensitivity list. "pClk"
> in routine ntyCounter line 18 in file
> '/home/yeowk/vhdl.dir/MyProj.dir/Vhdl.dir/arcCounter.vhd' (HDL-400)

> I thought that code (1) is the same as code (2) functionally:

> process -- Code(1)
> begin
> wait until rising_edge(clk);
> :
> :
> :
> end process;

> process(Clk) - Code(2)
> begin
> if rising_edge(Clk) then
> :
> :
> :
> end if;
> end process

> I check the Solvit in Synopsys but cannot find any workaround. Can
> someone enlightened why the above statement is not accepted in synthesis
> engine(particular Synopsys).

> By the way, code(2) pass the synthesis without warning! Can you explain?

Well, the equivalent of code(2) using a wait is the subtley different
from your code(1):

process
begin
if rising_edge(clk) then
:
:
end if;
wait on clk;
end process;

Why don't you want to use the normal idiom? Or is it being converted
from verilog?

-- Senior Design Engineer
-- Cadence Design Systems, Alba Campus, Livingston EH54 7HH, Scotland
-- Phone: +44 1506 595360 Fax: +44 1506 595959

Sun, 20 Oct 2002 03:00:00 GMT

Andrew Inc
#3 / 13

Wait until statement problem in synthesis

Quote:

> > I wonder why wait until statement when used in a process can generate a
> > warning of :
> > Warning: Clock signal is not in the sensitivity list. "pClk"

looks like a error in the name "pClk" not "Clk".

Quote:

> > I thought that code (1) is the same as code (2) functionally:

So do I and the training companies

Quote:

> > By the way, code(2) pass the synthesis without warning! Can you explain?

Clock name difference

Quote:

> Well, the equivalent of code(2) using a wait is the subtley different
> from your code(1):
> Why don't you want to use the normal idiom?

Training companies like Dulos say the 2 are equivalent.

Andrew Ince, BAE SYSTEMS, Basildon

Mon, 21 Oct 2002 03:00:00 GMT

Andrew MacCormac
#4 / 13

Wait until statement problem in synthesis

Quote:

> > > I thought that code (1) is the same as code (2) functionally:
> So do I and the training companies

> > Why don't you want to use the normal idiom?
> Training companies like Dulos say the 2 are equivalent.

The VHDL LRM says in Section 9.2 that:

"If a sensitivity list appear following the reserved word process, then
the process statement is assumed to contain an implicit wait statement
as the LAST statement of the process statement part"

And rising_edge(s) is not just s'event and s='1' but also
s'last_value='0' as defined in IEEE standard 1164. So the two bits of
code differ subtely for at least simulation. Synthesis equivalence
probably depends on the implementation of the synthesis program.

-- Senior Design Engineer
-- Cadence Design Systems, Alba Campus, Livingston EH54 7HH, Scotland
-- Phone: +44 1506 595360 Fax: +44 1506 595959

Mon, 21 Oct 2002 03:00:00 GMT

Walt Malinowsk
#5 / 13

Wait until statement problem in synthesis

All wait statements are for testbenches only, a synthesys tool can't do a
wait.

Walt

Quote:

> Hi,

> I wonder why wait until statement when used in a process can generate a
> warning of :

> Warning: Clock signal is not in the sensitivity list. "pClk"
> in routine ntyCounter line 18 in file
> '/home/yeowk/vhdl.dir/MyProj.dir/Vhdl.dir/arcCounter.vhd' (HDL-400)

> I thought that code (1) is the same as code (2) functionally:

> process -- Code(1)
> begin
> wait until rising_edge(clk);
> :
> :
> :
> end process;

> process(Clk) - Code(2)
> begin
> if rising_edge(Clk) then
> :
> :
> :
> end if;
> end process

> I check the Solvit in Synopsys but cannot find any workaround. Can
> someone enlightened why the above statement is not accepted in synthesis
> engine(particular Synopsys).

> By the way, code(2) pass the synthesis without warning! Can you explain?

> Yeo Wee Kwong, Sky (Mr)

Thu, 24 Oct 2002 03:00:00 GMT

#YEO WEE KWONG
#6 / 13

Wait until statement problem in synthesis

Not fully true.
the following is synthesisable by FPGA express.

process
begin
wait until a= '1';
c4 <= not a;
end process;

Yeo Wee Kwong, Sky (Mr)

Quote:

-----Original Message-----

Posted At: Monday, May 08, 2000 3:01 AM
Posted To: comp.lang.vhdl
Conversation: Wait until statement problem in
synthesis
Subject: Re: Wait until statement problem in
synthesis

All wait statements are for testbenches only, a
synthesys tool can't do a
wait.

Walt

message

> Hi,

> I wonder why wait until statement when used in a
process can generate a
> warning of :

> Warning: Clock signal is not in the sensitivity list.
"pClk"
> in routine ntyCounter line 18 in file

'/home/yeowk/vhdl.dir/MyProj.dir/Vhdl.dir/arcCounter.vhd' (HDL-400)

> I thought that code (1) is the same as code (2)
functionally:

> process -- Code(1)
> begin
> wait until rising_edge(clk);
> :
> :
> :
> end process;

> process(Clk) - Code(2)
> begin
> if rising_edge(Clk) then
> :
> :
> :
> end if;
> end process

> I check the Solvit in Synopsys but cannot find any
workaround. Can
> someone enlightened why the above statement is not
accepted in synthesis
> engine(particular Synopsys).

> By the way, code(2) pass the synthesis without
warning! Can you explain?

> Yeo Wee Kwong, Sky (Mr)

Fri, 25 Oct 2002 03:00:00 GMT

#YEO WEE KWONG
#7 / 13

Wait until statement problem in synthesis

Hi,

I summarised the discussion as below to close the whole topic:

1) Discussion Topic:
* Wait until statement warning in Synthesis for Synopsys DC, FPGA
express

Problem:
* Generate a HDL-400 warning

Summary of Solutions:
* Use the sensitivity list process instead of wait until statement

Conclusion:
* Synopsys does not support rising_edge function
* Use sensitivity list process instead of wait until statement
* Wait until statement usage does not generate warning for other
synthesis engines like Synplify and Leonardo Spectrum.
* Wait until clk = '1' and clk'event will still generate the same
warning as wait until
rising_edge(clk);
* The two construct generate the same synthesis result despite the
warning.(Tested with FPGA express and Leonardo)

Yeo Wee Kwong, Sky (Mr)

Words Of Wisdom:
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
"Let it be the way you want to be!. Amen!
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~

Sun, 27 Oct 2002 03:00:00 GMT

Alan Fitc
#8 / 13

Wait until statement problem in synthesis

Quote:

>Hi,

>I summarised the discussion as below to close the whole topic:

>1) Discussion Topic:
>* Wait until statement warning in Synthesis for Synopsys DC, FPGA
>express

>Problem:
>* Generate a HDL-400 warning

>Summary of Solutions:
>* Use the sensitivity list process instead of wait until statement

>Conclusion:
>* Synopsys does not support rising_edge function

This is incorrect. Versions of Synopsys after 98.08 (I think) support
rising_edge.

Quote:

>* Use sensitivity list process instead of wait until statement

wait until is fine - HDL-400 is just a warning, it's not an error!

Quote:

>* Wait until statement usage does not generate warning for other
>synthesis engines like Synplify and Leonardo Spectrum.
>* Wait until clk = '1' and clk'event will still generate the same
>warning as wait until
> rising_edge(clk);
>* The two construct generate the same synthesis result despite the
>warning.(Tested with FPGA express and Leonardo)

>Yeo Wee Kwong, Sky (Mr)

>Words Of Wisdom:
>~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
> "Let it be the way you want to be!. Amen!
>~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~

--
Alan Fitch
DOULOS Ltd.
Church Hatch, 22 Market Place, Ringwood, BH24 1AW, Hampshire, UK

Fax: +44 (0)1425 471 573
** Visit THE WINNING EDGE www.doulos.com **

Sun, 27 Oct 2002 03:00:00 GMT

Chandramohan Satees
#9 / 13

Wait until statement problem in synthesis

Dear Sky,

As per the LRM for VHDL wait statements will not be synthesised. DC will
not synthesise
them. What you could probably do is

process(clk)
begin
if (clk'event and clk='1') then
---make sure to have your sequential statements
end process;

This would be a sequential process. You could possibly use another
concurrent process for your concurrent statements and assignements.

Regards

Sateesh

Quote:

> Not fully true.
> the following is synthesisable by FPGA express.

> process
> begin
> wait until a= '1';
> c4 <= not a;
> end process;

> Yeo Wee Kwong, Sky (Mr)

> -----Original Message-----

> Posted At: Monday, May 08, 2000 3:01 AM
> Posted To: comp.lang.vhdl
> Conversation: Wait until statement problem in
> synthesis
> Subject: Re: Wait until statement problem in
> synthesis

> All wait statements are for testbenches only, a
> synthesys tool can't do a
> wait.

> Walt

> message

> > Hi,

> > I wonder why wait until statement when used in a
> process can generate a
> > warning of :

> > Warning: Clock signal is not in the sensitivity list.
> "pClk"
> > in routine ntyCounter line 18 in file

> '/home/yeowk/vhdl.dir/MyProj.dir/Vhdl.dir/arcCounter.vhd' (HDL-400)

> > I thought that code (1) is the same as code (2)
> functionally:

> > process -- Code(1)
> > begin
> > wait until rising_edge(clk);
> > :
> > :
> > :
> > end process;

> > process(Clk) - Code(2)
> > begin
> > if rising_edge(Clk) then
> > :
> > :
> > :
> > end if;
> > end process

> > I check the Solvit in Synopsys but cannot find any
> workaround. Can
> > someone enlightened why the above statement is not
> accepted in synthesis
> > engine(particular Synopsys).

> > By the way, code(2) pass the synthesis without
> warning! Can you explain?

> > Yeo Wee Kwong, Sky (Mr)

Mon, 28 Oct 2002 03:00:00 GMT

Alan Fitc
#10 / 13

Wait until statement problem in synthesis

Quote:

>Dear Sky,

>As per the LRM for VHDL wait statements will not be synthesised. DC will
>not synthesise
>them. What you could probably do is

This is not true. The LRM says absolutely nothing about synthesis - that
is up to the synthesis tool vendors.

You can use wait statements, it just depends on the synthesis tool. In
fact some tools will support multiple "wait until" statements to produce
state machines (e.g. Spectrum).

However it is fair to say that "wait for" is not supported by synthesis
tools.

Quote:

>process(clk)
> begin
> if (clk'event and clk='1') then
> ---make sure to have your sequential statements
> end process;

>This would be a sequential process.

All statements executed after the 'begin' of a process are sequential. A
process statement itself is concurrent.

<snip>

Alan
--
Alan Fitch
DOULOS Ltd.
Church Hatch, 22 Market Place, Ringwood, BH24 1AW, Hampshire, UK

Fax: +44 (0)1425 471 573
** Visit THE WINNING EDGE www.doulos.com **

Mon, 28 Oct 2002 03:00:00 GMT