Speed of VHDL simulators 
Author Message
 Speed of VHDL simulators

There seem to be quite a lot of good VHDL compilers around at the moment.
Does anyone have any figures for their relative speeds ?

We are moving from a (very) fast in-house simulation environment, and
are worried that things that now take a day to simulate might take 4 or 5
days in VHDL.  Does anyone have any experience of this kind of problem ?

I have an article by David Wharton from June 14 edition of Electronic
Engineering Times, which gives a good comparison of a number of simulators.
According to this article, the fastest way to go is Verilog.

To benchmark VHDL simulators properly, a suite of designs would be necessary,
as some designs create more problems than others.

--
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John Webster                                     ARM Ltd.
                 Phone   0223 813000             Swaffham Bulbeck

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Mon, 22 Jan 1996 23:15:31 GMT  
 Speed of VHDL simulators

JW> Does anyone have any figures for their relative speeds ?
Probably, but don't trust them.  Certainly not from the vendors (no offense
implied, of course).  It is always case dependent.  Look at the results that are
available out there, but make sure you get evaluation copies of the actual
tools from the top two or three vendors, and apply them against critical
portions of your design.  The latest tools out there are fancy and fast, but
break a lot, and can be exceedingly limited in what they model.

JW> We are moving from a (very) fast in-house simulation environment, and
JW> are worried that things that now take a day to simulate might take 4 or 5
JW> days in VHDL.  Does anyone have any experience of this kind of problem ?
Dunno.  How long does it take now?  "fast" to 4-5 days isn't correlated.

Yes, we run long simulations here.  A lot of companies out here will be
running multi-day simulations, but that is usually batched off during
large regression suites, and we aren't particularily worried about the
speed.

JW> I have an article by David Wharton from June 14 edition of Electronic
JW> Engineering Times, which gives a good comparison of a number of simulators.
JW> According to this article, the fastest way to go is Verilog.
Simulation speed, mind you.  Don't forget there are oodles of other
factors involved in efficient design.  And with the good design
methodologies, you'll see that the actual simulation time is not
necessarily the major contributor.  You'll spend more time writing
comprehensive test suites, for instance.  And part of that is having
tools to help you write those tests and analyze the results.  Along with
that goes the documentation style, ease of tool use, schematic editors,
etc.  Up above you called your in-house stuff an "environment."  That's
what I'm talking about, not just the simulation engines.

Fast engines are cheap and plentiful for a plethora of languages. But
the environment is what makes efficient and effective system design
possible.  If you're in a "make it and throw away" design environment,
the other, faster simulation tools might be very appropriate.  Don't
limit yourself to just Verilog, either.

JW> To benchmark VHDL simulators properly, a suite of designs would be
JW> necessary, as some designs create more problems than others.
Some people are trying to put such things together.  I have yet to see
comprehensive results.  



Tue, 23 Jan 1996 02:00:17 GMT  
 Speed of VHDL simulators

Quote:

> There seem to be quite a lot of good VHDL compilers around at the moment.
> Does anyone have any figures for their relative speeds ?

> We are moving from a (very) fast in-house simulation environment, and
> are worried that things that now take a day to simulate might take 4 or 5
> days in VHDL.  Does anyone have any experience of this kind of problem ?

> I have an article by David Wharton from June 14 edition of Electronic
> Engineering Times, which gives a good comparison of a number of simulators.
> According to this article, the fastest way to go is Verilog.

VHDL simulators do a lot of things that some more traditional simulators don't
do.  In order to have these features available, you have to pay a non-neglible
performance penalty.
You describe your internal simulator as "very fast", and wonder if you might
pay a four to five x performance penalty if you move to a software VHDL
simulator.  Bluntly, if your present simulator is as fast as you think it is,
you might easily have to pay this sort of performance penalty.
However, as another poster alluded, speed isn't everything.  The environment
that you do you development plays a significant role in the amount of time
that it takes to develop a product (particularly a new product).

TJ
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Tue, 23 Jan 1996 06:11:10 GMT  
 
 [ 3 post ] 

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