How to reduce ringing/ground bounce from FPGA output pin? 
Author Message
 How to reduce ringing/ground bounce from FPGA output pin?

Hi everyone.

I would like to know if there is a way to eliminate ringing/ground bounce
from a signal that is being output by the FPGA.

The design that our research team has built requires the use of a divided
clock (1/8 generated via VHDL code) that must be fed to a bit error rate
test system through a physical cable.  The problem we see at the divided
clock output is a lot of ringing (with a negative spike of 2V).  We are not
sure if the problem is directly related to any form of ground bounce, but
any suggestions for configuring the FPGA (either by configuring the IOBs
or adding external capacitors or an RC network) that could reduce these
unwanted oscillations are greatly welcome.  We have tried both TTL and
CMOS outputs and the results are just as bad in both cases.

Our FPGA is a Xilinx 4028E-3HQ240, and the divided clock can be chosen
directly from a header or an SMB connector.  Our input clock is TTL
(0-5V) and is quite clean.

Thanks in advance for any help.
--
Nestor Caouras



Sat, 10 Mar 2001 03:00:00 GMT  
 How to reduce ringing/ground bounce from FPGA output pin?
The ringing is probably because the cable is not
terminated properly.  The easiest way to terminate
it is with "reverse termination".  Add a small
resistor (chip resistor or 1/10 watt leaded
resistor) in series and as close as possible to
the FPGA pin. The value should be close to the
impedance of the cable you are driving.  For
instance, if you are driving 50 ohm cable, then
use a 47 ohm resistor. If it still rings, then
increase the value.  If it slows down the edge too
much, then lower the value.

The important thing is to measure the waveform at
the destination, that is, at the receiving end. If
you measure at the resistor, you'll see an ugly
waveform. One easy way to check the waveform is to
just run the cable directly into a high impedance
scope input, then you won't be fooled by the long
ground wire on your scope probe.

Quote:

> Hi everyone.

> I would like to know if there is a way to eliminate ringing/ground bounce
> from a signal that is being output by the FPGA.

> The design that our research team has built requires the use of a divided
> clock (1/8 generated via VHDL code) that must be fed to a bit error rate
> test system through a physical cable.  The problem we see at the divided
> clock output is a lot of ringing (with a negative spike of 2V).  We are not
> sure if the problem is directly related to any form of ground bounce, but
> any suggestions for configuring the FPGA (either by configuring the IOBs
> or adding external capacitors or an RC network) that could reduce these
> unwanted oscillations are greatly welcome.  We have tried both TTL and
> CMOS outputs and the results are just as bad in both cases.

> Our FPGA is a Xilinx 4028E-3HQ240, and the divided clock can be chosen
> directly from a header or an SMB connector.  Our input clock is TTL
> (0-5V) and is quite clean.

> Thanks in advance for any help.
> --
> Nestor Caouras




Sun, 11 Mar 2001 03:00:00 GMT  
 How to reduce ringing/ground bounce from FPGA output pin?

Quote:

> Hi everyone.

> I would like to know if there is a way to eliminate ringing/ground bounce
> from a signal that is being output by the FPGA.

> The design that our research team has built requires the use of a divided
> clock (1/8 generated via VHDL code) that must be fed to a bit error rate
> test system through a physical cable.  The problem we see at the divided
> clock output is a lot of ringing (with a negative spike of 2V).  We are not
> sure if the problem is directly related to any form of ground bounce, but
> any suggestions for configuring the FPGA (either by configuring the IOBs
> or adding external capacitors or an RC network) that could reduce these
> unwanted oscillations are greatly welcome.  We have tried both TTL and
> CMOS outputs and the results are just as bad in both cases.

> Our FPGA is a Xilinx 4028E-3HQ240, and the divided clock can be chosen
> directly from a header or an SMB connector.  Our input clock is TTL
> (0-5V) and is quite clean.

> Thanks in advance for any help.
> --
> Nestor Caouras


Assuming the noise generated from the output is due to reflection and
not a noisy input(make sure your inputs are not glitchy) then the
reflection(or even ground bounce) will be proportional not to the
frequency of your output signal but the slew rate of the edges...You'll
need to either slow your edges down(as some fpgas vendors allow--such as
Altera's turbo bit) or via the tuning of your transmission line...A
previous post explaining the use of a source/series resistor is a good
starting point...A good reference on the subject is a book titled,

Howard(Phd) and Martin (Phd),"High Speed Digital Design: A Handbook of
Black Magic"

I hope this helps,

Professionally yours,

Joe



Mon, 12 Mar 2001 03:00:00 GMT  
 How to reduce ringing/ground bounce from FPGA output pin?
Thanks to everyone who has suggested some solutions. I will try the
simpler ones first.

Regards.

Nestor



Tue, 13 Mar 2001 03:00:00 GMT  
 
 [ 4 post ] 

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