Cadence User Group Conference 
Author Message
 Cadence User Group Conference

************************************************
Please distribute this within your organization!

Thanks,
Peter Stokes,
Communications Officer
International Cadence User Group

************************************************

You're invited to attend the 1994
International Cadence User Group Conference

Dear Fellow Cadence User:
This is your invitation to come meet Cadence's Executive Staff, to talk
with key marketing and research and development staff from Cadence, to
discuss your problems and find solutions, to make important contacts with
other users, and to view products from over 40 third-party vendors.

It's time for the 1994 International Cadence Users Conference. The ICu
board has worked hard all year preparing for this event. We surveyed users
and came up with what we believe to be an outstanding agenda. We kept the
old stand-bys such as technical papers, question and answer sessions in
each SIG, the Vendor Fair and training sessions at the end of the
conference. We also kept items that worked well last year, such as the
Executive Staff question and answer session, the Listening Booth, and the
Service Booths. Then we added a few new items such as App Notes Live! where
there will be Cadence Application Engineers showing problems and solutions
on the current release of software.

We hope you will join us, your fellow users, in attending this year's
conference.

Sincerely,
Chuck Phillips
ICu Chair

Conference Highlights

*  Technical Papers - Hear expert users share personal technical
experience. oCadence Night - Demos, New Product Presentations, Food, Music,
and Prizes.

*  App Notes Live! - Cadence AEs will present on-line problem/ resolution
scenarios for each Special Interest Group.

*  Cadence On-Line! - Cadence technical people and machines available for
your questions.

*  Cadence Listening Booth - Take the opportunity to talk one on one with
Cadence.

*  Vendor Fair - Come enjoy the great food and interact with over 40 vendors.

*  Customer Support Focus Groups - Take part in shaping the future of
Cadence Customer Support. Cadence is looking for volunteers to participate
in focus groups which will impact service and support for the future.
Indicate your interest on the registration form.

*  Top 10 Report- Find out how Cadence responded to the '93 Top 10 Issues.
Conference attendees will again construct the list of the Top 10 Issues
Cadence will focus on in '95.

*  Tutorial Day - Thursday, October 13 is a Tutorials Only day with 2 full
day and 3 half day tutorials being offered. Space is limited, so sign up
early. (See registration form at the back of this booklet).

*  Panels
--Customer Service Panel --Cadence Executive Panel --Special Interest Group
Technical Panels

*  Service Booths
--SourceLink --Educational Services --Applications Services --Support
Services --Documentation --and more!

*  Birds of a Feather - Networking and information sharing with your peers.

Saturday, October 8, 1994
5:00 - 9:00     Hotel Check In & Registration

General session
Sunday, October 9, 1994
8:00 - 10:00    Registration
10:00 - 10:30   ICu Welcome
                Top 10 Report Card
10:30 - 11:30   Joe Costello, President & CEO
                Cadence Design Systems, Inc.
                Keynote Speaker
11:30 - 12:00   Leonard Liu, COO
                Cadence Design Systems, Inc.
12:00 - 1:00    Lunch & Cadence Listening Booth
1:00 - 2:30     Customer Service Panel
                Q&A Session
2:30 - 3:00     Break
3:00 - 4:00     IC, CAE, PCB/MCM, and System Admin SIGS
                (See detailed agendas following)
4:30 - 5:00     Break
5:00 - 9:00     Cadence Night
                * Demos
                * Product Presentations
                * Dinner & Great Music

IC Special Interest Group Detailed Agenda
Sunday, October 9, 1994
3:00 - 4:30     IC SIG Business
5:00 - 9:00     Cadence Night

IC Special Interest Group Detailed Agenda
Monday, October 10, 1994
8:00 - 8:30     Using Cadence In the Educational Environment
                Gregory Sajdak, Michael Celetti
                University of Colorado
8:30 - 9:00     A Generic Technical Environment for
                Design Framework II Tools
                Peter Stokes,
                Canadian Microelectronics Corporation
9:00 - 9:15     A Method to Combine Edge and Extend Netlists
                Abraham Mizrahi, National Semiconductor
9:30 - 10:00    Break
10:00 - 12:00   IC Technical Panel
                Q&A Session
12:00 - 1:00    Lunch & Cadence Listening Booth
1:00 - 3:00     Technical Marketing Presentations
                * Analog Artist Design System
                * Layout Verification
                * IC Place & Route
                * Design Framework II
3:00 - 3:30     Break
3:30 - 5:30     Birds of a Feather

IC Special Interest Group Detailed Agenda
Tuesday, October 11, 1994
8:00 - 8:30     Connect By Name Checker
                Jim Newton, Intel
8:30 - 9:00     Graphic Data Mapper
                Jim Newton, Intel
9:00 - 9:30     Using Design Flows to Simplify
                the Layout Verification Process
                Mark Snowden, Harris
9:30 - 10:00    Generating Bond Diagram for
                Packaged IC Verification
                Steve Majors, Harris
10:00 - 10:30   Break
10:30 - 11:30   E-staff Interactive Session
11:30 - 1:00    Lunch Top 10 Intake & Board Nominations
1:00 - 1:30     Multiple Supplies Using Cell Ensemble
                Place and Route
                Dale Thompson, Harris
1:30 - 1:45     Auto Guardbanding Using Cell Ensemble
                Place & Route
                Dale Thompson, Harris
1:45 - 2:30     Turning QPlace For Highly Congested Design
                Pat Catapano, Motorola
2:30 - 3:00     Break
3:00 - 3:30     Analog Layout Using Virtuoso,
                Dracula and Inquery
                Paul Mason, Analog Development
3:00 - 4:15     Adaptive Routing
                Dr.{*filter*} Newman, Florida Institute of Technology
4:15 - 4:45     System Level Signal Analysis-A Tester Chip
                Jose Roberto de Almeida Amazonas, Quickchip
5:00 - 9:00     Vendor Fair

IC Special Interest Group Detailed Agenda
Wednesday, October 12, 1994
8:00 - 9:30     IC App Notes Live!
9:30 - 10:00    Break
10:00 - 10:15   Hspice View Creation Utility
                Shantanu Ganguly, Motorola
10:15 - 10:45   Behavi{*filter*}Modeling of Nonlinear Magnetics Using
                Cadence AHDL
                Mark Williams, Harris
10:45 - 12:00   TBD
12:00 - 1:00    Lunch Top Ten Voting & Board Elections
                Cliff Cummings, Qualis Design Corporation Lunch Speaker
1:00 - 2:30     IC SIG Business
2:30 - 3:00     Break
3:00 - 4:00     Open
4:00 - 5:00     General Session
                Final Top 10
                Best Speaker Awards

CAE Special Interest Group Detailed Agenda
Sunday, October 9, 1994
3:00 - 4:30     Digital Technical Panel
4:30 - 5:00     Break
5:00 - 9:00     Cadence Night

CAE Special Interest Group Detailed Agenda
Monday, October 10, 1994
8:00 - 9:30     Digital SIG Business
9:30 - 10:00    Break
10:00 - 10:45   System Design Using Top Down Design
                Shala Napier, Cadence Design Systems, Inc.
10:45 - 11:15   Plotting Hierarchical Design without Flattening
                Tom Kohl, LTX
11:15 - 11:30   Xilinx Actel Back Annotation
                Buck Titherington, JPL
11:30 - 12:00   Composer to Concept Symbol Conversion
                Mike Stanley, Motorola
12:00 - 1:00    Lunch & Listening Booth
1:00 - 3:00     Technical Marketing Presentations
                * Analog Workbench
                * HDL/VHDL
                * Front End Board
                * HDL/VHDL
3:00 - 3:30     Break
3:30 - 5:30     Birds of a Feather

CAE Special Interest Group Detailed Agenda
Tuesday, October 11, 1994
8:00 - 8:30     Utilities Implementing an Expert System to Improve the
                Concept/Allegro Transition
                Ike Ikizyan, TRW
8:30 - 9:00     Reference Designator Management in Concept
                Devin Barrett, Fluke Manufacturing
9:00 - 9:30     Methodology for the Development of a State Average
                PWM IC Models for use in Analog Workbench
                Andrew Bell, ITT
9:30 - 10:00    tbd
10:00 - 10:30   Break
10:30 - 11:30   E-staff Interactive Session
11:30 - 1:00    Lunch & Listening Booth
                Top 10 Intake & Board Nominations
1:00 - 1:45     Using VHDL Beyond Synthesis
                Sanjay Sawant, Cadence Design Systems, Inc.
1:45 - 2:30     Concept to Verilog Using Verilink
                Cliff Cummings, Qualis Design Corporation
2:30 - 3:00     Break
3:00 - 3:45     Board Preplacement Using Concept
                Ken Lehto, Magnavox
3:45 - 4:30     Two Approaches to Global PPTs
                Rick Munden, TRW
5:00 - 9:00     Vendor Fair

CAE Special Interest Group Detailed Agenda
Wednesday, October 12, 1994
8:00 - 9:30     Digital SIG Business
9:30 - 10:00    Break
10:00 - 12:00   App Notes Live!
12:00 - 1:00    Lunch Top Ten Voting & Board Elections
                Cliff Cummings, Qualis Design Corporation Lunch Speaker
1:00 - 1:45     Initializing a Concept to Verilog and Xilinx Design
                Directory Using "make_environment"
                Cliff Cummings, Qualis Design Corporation
1:45 - 2:30     TBD
2:30 - 3:00     Break
3:00 - 3:30     Library Update
                Cadence Design Systems, Inc.
3:30 - 4:00     TBD
4:00 - 5:00     General Session
                Final Top 10
                Best Speaker Awards

PCB/MCM Special Interest Group Detailed Agenda
Sunday, October 9, 1994
3:00 - 4:30     PCB/MCM SIG Business
4:30 - 5:00     Break
5:00 - 9:00     Cadence Night

PCB/MCM Special Interest Group Detailed Agenda
Monday, October 10, 1994
8:00 - 8:30     The PERL Connection
                David Warner-Murray, Fluke Corp
8:30 - 9:00     New Photo Plotter Formats
                Mark Layden, Cadence Design Systems, Inc.
9:00 - 9:30     Front-to-Back Concept-Allegro Integration
                Brian Jackson, Cadence Design Systems, Inc.
9:30 - 10:00    Break
10:00 - 12:00   PCB/MCM Technical Panel
12:00 - 1:00    Lunch
1:00 - 3:00     Technical Marketing Presentations
                * PCB   * SigNoise/Thermal
                * MCM   * HDL/VHDL
3:00 - 3:30     Break
3:30 - 5:30     Birds of a Feather

PCB/MCM Special Interest Group Detailed Agenda
Tuesday, October 11, 1994
8:00 - 9:00     Signal Integrity Issues Primer for Non-EEs
                Ken Willis, Cadence Design Systems, Inc.
9:00 - 9:30     tbd
9:30 - 10:00    How to Use the Diagonal Router in Allegro
                Buck Titherington, JPL
10:00 - 10:30   Break
10:30 - 11:30   E-staff Interactive Session
11:30 - 1:00    Lunch, Top 10 Intake & Board Nominations
1:00 - 2:00     How DF/SigNoise Works
                Ken Willis, Cadence Design Systems, Inc.
2:00 - 2:30     How to Use/Submit Programs to the
                Shareware Directory
                Ed Acherson, Cadence Design Systems, Inc.
2:30 - 3:00     Break
3:00 - 4:00     Overview of MCM Technologies and
                How to Set Up in Allegro MCM
                Ed Clark, Cadence Design Systems, Inc.
4:00 - 5:00     Techniques for Manual Placement
                Phil Arana, Ph.D., Cadence Design Systems, Inc.
5:00 - 9:00     Vendor Fair

PCB/MCM Special Interest Group Detailed Agenda
Wednesday, October 12, 1994
8:00 - 9:30     PCB SIG Business
9:30 - 10:00    Break
10:00 - 11:00   Thermal Integrity Primer for Non-Thermal Experts
                Ted Frederick, Cadence Design Systems, Inc.
11:00 - 11:20   How to Share Pin Escapes and How to Use the Delay Rule
                Paul Musto, Cadence Design Systems, Inc.
11:20 - 12:00   Getting the Most Out of Allegro and Prance-XL Auto
                Routers
                Ed Acherson, Cadence Design Systems, Inc.
12:00 - 1:00    Lunch, Top Ten Voting & Board Elections
                Cliff Cummings, Qualis Design Corp., Lunch Speaker
1:00 - 2:30     PCB/MCM App Notes Live!
2:30 - 3:00     Break
3:00 - 3:15     Review of How Best to Use Constraints
                Paul Musto, Cadence Design Systems, Inc.
3:15 - 3:30     How  to View Thermal Reliefs
                Ed Acherson, Cadence Design Systems, Inc.
4:00 - 5:00     General Session
                Final Top 10 & Best Speaker Awards

System Admin Special Interest Group
Monday, October 10, 1994
8:00 - 9:00     Technical Overview of Cadence Plotting Utility
                Pat Sheridan & Tim Marriott,
                Cadence Design Systems, Inc.
9:00 - 9:30     Automating System Administration Tasks
                Kathryn Krenn, E-Systems
9:30 - 10:00    Break
10:00 - 12:00   Open
12:00 - 1:00    Lunch & Listening Booth
1:00 - 3:00     Technical Marketing Presentations
                * DSP Design
                * Libraries
                * Design Framework II
                * PIC Designer
3:00 - 3:30     Break
3:30 - 5:30     Birds of a Feather

System Admin Special Interest Group
Tuesday, October 11, 1994
8:00 - 10:00    Framework Technical Panel
10:00 - 10:30   Break
10:30 - 11:30   E-staff Interactive Session
11:30 - 1:00    Lunch Top 10 Intake & Board Nominations
1:00 - 1:45     tbd
1:45 - 2:00     Useful postscript Programming
                Arn Buck, Data Switch
2:15 - 2:30     Genspice - A Better Office
                Steven Ma, Siemens
2:30 - 3:00     Break
3:00 - 5:00     System Administration Technical Panel
5:00 - 9:00     Vendor Fair

System Admin Special Interest Group
Wednesday, October 12, 1994
10:00 - 10:30  SKILL Function Headers Promote
                Development Team
                Steve Major, Harris
10:30 - 11:00   Procedural Data Storage Using SKILL
                Steven G. Esposito, Cadence Design Systems, Inc.
11:00 - 11:30   tbd
11:30 - 12:00   Open
12:00 - 1:00    Lunch Top Ten Voting & Board Elections
                Cliff Cummings, Lunch Speaker
1:00 - 2:30     Open
2:30 - 3:00     Break
3:00 - 4:00     Framework App Notes Live!
4:00 - 5:00     General Session
                Final Top 10 & Best Speaker Awards

Technical Tutorials--Thursday, October 13, 1994 This is a Tutorials Only
day for the user group conference. This year the conference features 2 full
day and 3 half day tutorials. To register, see registration form at the end
of this message.
Cost: Full Day-$50 Half Day-$25

Class Syllabi
1. Setting Up and Managing a Design Framework II Technology File and a
Design Library Half Day-$25
*Creating a Library
        -Contents of a library
        -The library structure in Design Framework II and in UNIX
        -Defining the access permissions; access for edits in progress
        -Creating a journal

*Managing Your Library
        -Defining a methodology for design library management
        -Identifying critical operations
        -Using SKILL triggers for updating the journal, to define access
control, to set UNIX permissions
        -Modifying the library Browser menus to enforce the methodology
        -Customizing the startup file .cdsinit to set up your methodology

* Technology File, Understanding the Terminology
        -Defining a methodology for using and updating technology files
        -Partitioning your source technology data: layers, displays,
plotter colors, rules, layer properties, symbolic devices
        -Using the UNIX "make" utility to manage your source data
        -Keeping your library synchronized with the source technology
        -Defining user preferences
        -Customizing the start up file .cdsinit to set up your methodology
* Sample SKILL Files
* Sample Startup Files
*Design Data Management
        - Useful Applications

2. Using top-down design methodology using Cadence tools
Full Day - $50
* These topics will be illustrated using a single design
        - Top-down design specification
        - Design entry
        - Behavi{*filter*}description
        - Design Verification
        - Design Implementation
        - Post Synthesis Analysis
        - Floorplanning
        - IC layout
        - IC verification
        - Backannotation from the physical design system
        - Exporting ASIC/PIC to board design
        - System level verification
        - Placement and Routing
        - Postlayout Simulation
        - Manufacturing

3. Advanced SKILL
Half Day - $25
* Advanced list construction
        - Map functions
        - How are lists stored in virtual memory
        - Destructive list operation
* SKILL Macros
        - Building SKILL code from templates
        - Defining a macro
* Data Structures
        - defstructs
        - Association list
        - Association tables
        - Comparing the -> and ~> operators
* SKILL development environment
        - The SKILL compiler
        - Setting breakpoints
        - The SKILL profiler
* Scheme
        - What key features of this language will be added to SKILL in a
future release

4. Verification
Full Day-$50
* Dracula to CDC Flow
* LPE/PRE
* Distributed Dracula
* Metal Migration
* BlackBoxLVS
* Verilog and LOGLVS
* CDSIN
* CDLOUT
* GE/C3 to Dracula
* LVS Result Analysis
* Dracula vs. Diva Comparison
* Hands-on Exercises

5. Using SKILL in Allegro
(with excerpts of selected procedures)
 Half Day- $25

Existing procedures for Automatic Wire Bond Creation and Shielded Traces
will be provided with excerpts used for examples to create procedures using
SKILL in Allegro.
* Form Generation
* User Interface
* Database Query
* Database Synthesis

Hotel Information
Marriott Hotel
2700 Mission College Boulevard
Santa Clara CA 95052-8181
408-988-1500
Reservation FAX line - 408-970-6186
room rate: $109.00, per night, plus tax
Call or fax the hotel with your room requirements.

Travel Information
American or American Eagle Airlines is offering group discounts of 5% off
any published fare and 10% off coach fares. Certain restrictions apply.
Call 1(800) 526-4719 for airfare and rental car discount information. Ask
for International Cadence Users Group Discount.

Shuttle Transportation
The Santa Clara Marriott has provided a complimentary shuttle from the San
Jose Airport every half hour. There is a direct phone line to the hotel in
the baggage claim area. Shuttles for hire from the San Francisco airport
may be obtained by calling 24 hours in advance to the Airport Connection,
(408) 730-5555

Registration fees:
Before 9/9/94 - $350.00
After 9/9/94 - $400.00
On site (at registration desk) - $450.00
One day registration - $150.00
If you are a presenter, deduct $100.00 from your fee.

Complete the following.
Name:
Title:
Company:
Address:
Mail stop:
City:
State:
Zip:
Special interest group: IC      CAE     PCB/MCM         System Admin.

___Contact me regarding participation in Cadence Customer Support Focus Group

Tutorial Registration:
___ Setting Up and Managing a Design Framework II Technology File and A
Design Library  $25.00
___Top-down Design Methodology Using Cadence Tools $50.00
___Advanced SKILL       $25.00
___Verification $50.00
___Using SKILL in Allegro $25.00

Payment:
Conference Registration Fee:            $________
Technical Tutorial(s) Fee:              $________
Presenter Deduction (if applicable)     $ <100.00>
Total Due Cadence User Group:           $________
_______Enclosed is a company/personal check for:        $________
_______Charge conference fees to:
___American Express     ___Visa ___Master Card
Card Number__________________________Expires______
Signature__________________________________________

Mail or Fax to: Cadence User Group
c/o Meeting Planning & More
7043 E. Dreyfus Ave., Scottsdale, AZ 85254 (602) 596-9377
FAX (602) 596-9006

Cancellation Notice
Registration fee will be refunded for cancellations postmarked prior to
September 9, 1994. For cancellations made after September 9, 1994, the
registration fee, less $50.00, will be refunded.

updated 8/10/94



Thu, 06 Mar 1997 22:20:30 GMT  
 
 [ 1 post ] 

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