Variables in VHDL How are they synthesized? 
Author Message
 Variables in VHDL How are they synthesized?

Hi:)
   I was wondering if variables have any physical significance at all
in VHDL.I mean when you synthesize and translate the design to the
board what happens to the variables??How does VHDL handle variables?
Thanks:)

Harkirat



Wed, 13 Jul 2005 03:38:09 GMT  
 Variables in VHDL How are they synthesized?
Quote:
>  I was wondering if variables have any physical significance at all
>in VHDL.I mean when you synthesize and translate the design to the
>board what happens to the variables??How does VHDL handle variables?
>Thanks:)

In clocked processes, variables that are written BEFORE they are read
are usually treated as temporary computational values, and in synthesis
may represent a wire.  
If the variables are read first before being written, then they are registers
because they have to hold their values between clock. Thus,
process (clk) is
 variable v : std_logic; -- DO not initalize for synthesis
 variable k : std_logic;
begin
if clk'event and clk = '1';
  v := a or b;  -- v is a wire, it is written  first
  q <= v and c;  -- v is read here
  w <= k or q; -- w is a read ferore being written
        -- w is a register.
 end if;
-- Note some simulator may implement the variables as registers, and then
optimize them out later (this is for  variables that are written BEFORE they
are read).
....

In non clocked processes, variables that are written BEFORE they are read
are usually treated as temporary computational values, and in synthesis
may a wire.  If the variables are read first before being written, then they
are latches
because they have to hold their values.
----------------------------------------------------------------------------
Ben Cohen     Publisher, Trainer, Consultant    (310) 721-4830  

Author of following textbooks:
* Real Chip Design and Verification Using Verilog and VHDL, 2002 isbn
0-9705394-2-8
* Component Design by Example ",  2001 isbn  0-9705394-0-1
* VHDL Coding Styles and Methodologies, 2nd Edition, 1999 isbn 0-7923-8474-1
* VHDL Answers to Frequently Asked Questions, 2nd Edition, isbn 0-7923-8115
------------------------------------------------------------------------------



Wed, 13 Jul 2005 05:58:49 GMT  
 Variables in VHDL How are they synthesized?

Quote:

> Hi:)
>    I was wondering if variables have any physical significance at all
> in VHDL.

Yes. A variable could synthesize to nothing, a bus width, some gates, the
value on a bus, a counter, a shifter, or a RAM. It depends how you use them.

Quote:
> I mean when you synthesize and translate the design to the
> board what happens to the variables??How does VHDL handle variables?

Synthesis makes a netlist that simulates the same as your code.
Since variable values must be maintained between process invocations
registers may be inferred for variables used in clocked processes.

If you can imagine describing hardware algorithmically,
using variables will come naturally.

If you prefer to describe hardware at the gates and flops level,
variables will be more difficult, but there is no requirement
that you have to use them.

       -- Mike Treseler



Wed, 13 Jul 2005 06:11:52 GMT  
 Variables in VHDL How are they synthesized?

Quote:

> In clocked processes, variables that are written BEFORE they are read
> are usually treated as temporary computational values, and in synthesis
> may represent a wire.  
> If the variables are read first before being written, then they are registers
> because they have to hold their values between clock.

How about this,
in a clocked process, for variable a,b:
if xxx then
    a:= b;
else
    b:= a;
endif
c <= a or b;

Whether a and b are registers or not, what if xxx is constant false?

TT



Wed, 13 Jul 2005 10:27:49 GMT  
 Variables in VHDL How are they synthesized?
Quote:
>> In clocked processes, variables that are written BEFORE they are read
>> are usually treated as temporary computational values, and in synthesis
>> may represent a wire.  
>> If the variables are read first before being written, then they are
>registers
>> because they have to hold their values between clock.

>How about this,
>in a clocked process, for variable a,b:
>if xxx then
>    a:= b;
>else
>    b:= a;
>endif
>c <= a or b;

>Whether a and b are registers or not, what if xxx is constant false?

Whether xxx is true or false, one of the variables is read BEFORE it is
written.
Thus, in that case "a" is a register since it is read first when xxx if false.
Also, "b" is a register since it is read first when xxx is true.  
You need to consider ALL the paths.  
Thus, to reiterate the rule:
In clocked processes, variables that are written under ALL conditional paths
 BEFORE they are read are usually treated as temporary computational values,
and in synthesis may represent a wire.  
If the variables are read first in any of the conditional paths (if or case
statements)
BEFORE they being written, then they are registers because they have to hold
their values between clock.
---------------------------------------------------------------------------
Ben Cohen     Publisher, Trainer, Consultant    (310) 721-4830  

Author of following textbooks:
* Real Chip Design and Verification Using Verilog and VHDL, 2002 isbn
0-9705394-2-8
* Component Design by Example ",  2001 isbn  0-9705394-0-1
* VHDL Coding Styles and Methodologies, 2nd Edition, 1999 isbn 0-7923-8474-1
* VHDL Answers to Frequently Asked Questions, 2nd Edition, isbn 0-7923-8115
------------------------------------------------------------------------------


Thu, 14 Jul 2005 02:46:51 GMT  
 Variables in VHDL How are they synthesized?
How about

if false then
    a:= b;
...

Does this make b a register?

if the xxx below is a signal or variable, it is quite difficult to find
out whether xxx is constantly true or false for compilers -> usually
compiler does not deal with that. So, my answer to my own question is
that b would be treated as a register. What do you think?

TT

Quote:

>>>In clocked processes, variables that are written BEFORE they are read
>>>are usually treated as temporary computational values, and in synthesis
>>>may represent a wire.  
>>>If the variables are read first before being written, then they are

>>registers

>>>because they have to hold their values between clock.

>>How about this,
>>in a clocked process, for variable a,b:
>>if xxx then
>>   a:= b;
>>else
>>   b:= a;
>>endif
>>c <= a or b;

>>Whether a and b are registers or not, what if xxx is constant false?

> Whether xxx is true or false, one of the variables is read BEFORE it is
> written.
> Thus, in that case "a" is a register since it is read first when xxx if false.
> Also, "b" is a register since it is read first when xxx is true.  
> You need to consider ALL the paths.  
> Thus, to reiterate the rule:
> In clocked processes, variables that are written under ALL conditional paths
>  BEFORE they are read are usually treated as temporary computational values,
> and in synthesis may represent a wire.  
> If the variables are read first in any of the conditional paths (if or case
> statements)
> BEFORE they being written, then they are registers because they have to hold
> their values between clock.
> ---------------------------------------------------------------------------
> Ben Cohen     Publisher, Trainer, Consultant    (310) 721-4830  

> Author of following textbooks:
> * Real Chip Design and Verification Using Verilog and VHDL, 2002 isbn
> 0-9705394-2-8
> * Component Design by Example ",  2001 isbn  0-9705394-0-1
> * VHDL Coding Styles and Methodologies, 2nd Edition, 1999 isbn 0-7923-8474-1
> * VHDL Answers to Frequently Asked Questions, 2nd Edition, isbn 0-7923-8115
> ------------------------------------------------------------------------------



Fri, 15 Jul 2005 07:29:31 GMT  
 Variables in VHDL How are they synthesized?
Quote:
>if false then
>    a:= b;
>...

>Does this make b a register?

>if the xxx below is a signal or variable, it is quite difficult to find
>out whether xxx is constantly true or false for compilers -> usually
>compiler does not deal with that. So, my answer to my own question is
>that b would be treated as a register. What do you think?

The statement
  if false then
      a:= b;
will be ignored by the synthesis tool upon optimization because the condition
of the IF is always FALSE.  
On the other hand if you have
process  ( ...) is
begin
  some_var := y and z;
  if some_var then
    a := b; -- b is a variable
  end if;
....
Then b will be a register since the value of some_var may either be true ofr
false.
Re-read the rule that I wrote before.
---------------------------------------------------------------------------
Ben Cohen     Publisher, Trainer, Consultant    (310) 721-4830  

Author of following textbooks:
* Real Chip Design and Verification Using Verilog and VHDL, 2002 isbn
0-9705394-2-8
* Component Design by Example ",  2001 isbn  0-9705394-0-1
* VHDL Coding Styles and Methodologies, 2nd Edition, 1999 isbn 0-7923-8474-1
* VHDL Answers to Frequently Asked Questions, 2nd Edition, isbn 0-7923-8115
------------------------------------------------------------------------------


Sat, 16 Jul 2005 00:53:41 GMT  
 Variables in VHDL How are they synthesized?

Quote:

> On the other hand if you have
> process  ( ...) is
> begin
>   some_var := y and z;
>   if some_var then
>     a := b; -- b is a variable
>   end if;
> ....
> Then b will be a register since the value of some_var
> may either be true or false.

Assuming of course that the value of b affects
an output port somewhere in the process.

      -- Mike Treseler



Sat, 16 Jul 2005 02:26:04 GMT  
 Variables in VHDL How are they synthesized?

Quote:

> The statement
>   if false then
>       a:= b;
> will be ignored by the synthesis tool upon optimization because the condition
> of the IF is always FALSE.  
> On the other hand if you have
> process  ( ...) is
> begin
>   some_var := y and z;
>   if some_var then
>     a := b; -- b is a variable
>   end if;
> ....
> Then b will be a register since the value of some_var may either be true ofr
> false.
> Re-read the rule that I wrote before.

Ben, sorry for my stupidity. But what if
z<= not y;
Your some_var will never be true logically.

TT



Sat, 16 Jul 2005 08:40:06 GMT  
 Variables in VHDL How are they synthesized?

Quote:
>> begin
>>   some_var := y and z;
>>   if some_var then
>>     a := b; -- b is a variable
>>   end if;
>> ....
>> Then b will be a register since the value of some_var may either be true
>ofr
>> false.
>> Re-read the rule that I wrote before.

>Ben, sorry for my stupidity. But what if
>z<= not y;
>Your some_var will never be true logically.

Re-read the rule that I wrote before.
If, under all conditions, a variable is written before it is read it is not a
register or a latch.
if the synthesizer can determine thatn an object will never be used
(such as if false a <= b) then that statement is optimized out.
The rule is really very simple.  Is a variable has to hold its value between
clocks, then it is a register in a clocked process (or a latch in a non-clocked
process).
... END of STORY!!!!
Ben
---------------------------------------------------------------------------
Ben Cohen     Publisher, Trainer, Consultant    (310) 721-4830  

Author of following textbooks:
* Real Chip Design and Verification Using Verilog and VHDL, 2002 isbn
0-9705394-2-8
* Component Design by Example ",  2001 isbn  0-9705394-0-1
* VHDL Coding Styles and Methodologies, 2nd Edition, 1999 isbn 0-7923-8474-1
* VHDL Answers to Frequently Asked Questions, 2nd Edition, isbn 0-7923-8115
------------------------------------------------------------------------------


Sat, 16 Jul 2005 09:17:28 GMT  
 Variables in VHDL How are they synthesized?

Quote:
> If, under all conditions, a variable is written before it is read it is not a
> register or a latch.

Sorry, but "under all conditions" is a difficult thing to determine.
Just think about it. Satisfiable problem is one of the classic NP-hard
problem.

Quote:
> if the synthesizer can determine thatn an object will never be used
> (such as if false a <= b) then that statement is optimized out.
> The rule is really very simple.  

I just raised an extreme example. It is not always that simple. The
reason that I ask you repeatedly is because register is not like logic
that could be optimized easily later.

TT



Sat, 16 Jul 2005 11:44:29 GMT  
 Variables in VHDL How are they synthesized?

Quote:

> Sorry, but "under all conditions" is a difficult thing to determine.
> Just think about it. Satisfiable problem is one of the classic NP-hard
> problem.

That's why synthesis software is difficult to write
and why synthesis sometimes punts or hangs if you give
it code that is slightly too pathological.

With new engineering tools you figure out what works
and use that.

    -- Mike Treseler



Sun, 17 Jul 2005 02:02:09 GMT  
 Variables in VHDL How are they synthesized?

Quote:


>> Sorry, but "under all conditions" is a difficult thing to determine.
>> Just think about it. Satisfiable problem is one of the classic NP-hard
>> problem.

> That's why synthesis software is difficult to write
> and why synthesis sometimes punts or hangs if you give
> it code that is slightly too pathological.

That's not the reason why synthesis software is difficult to write.
You can test your synthesis software to see how it behaves. As far as I
tested, Design Compiler does not behave as Ben described.

TT



Sun, 17 Jul 2005 08:03:55 GMT  
 Variables in VHDL How are they synthesized?

Quote:

> That's not the reason why synthesis software is difficult to write.
> You can test your synthesis software to see how it behaves. As far as I
> tested, Design Compiler does not behave as Ben described.

I disagree. Post your code.
Remember that a variable or signal
without a flow to an entity output port
will synthesize nothing.

         -- Mike Treseler



Sun, 17 Jul 2005 13:58:08 GMT  
 Variables in VHDL How are they synthesized?
Hi ticktack,
    Can you post your tested code (copy & paste the vhdl file:entity,
architecture, process. Not just a description of what you did) ?
thank
Fe


Quote:


> >> Sorry, but "under all conditions" is a difficult thing to determine.
> >> Just think about it. Satisfiable problem is one of the classic NP-hard
> >> problem.

> > That's why synthesis software is difficult to write
> > and why synthesis sometimes punts or hangs if you give
> > it code that is slightly too pathological.

> That's not the reason why synthesis software is difficult to write.
> You can test your synthesis software to see how it behaves. As far as I
> tested, Design Compiler does not behave as Ben described.

> TT



Sun, 17 Jul 2005 23:02:35 GMT  
 
 [ 15 post ] 

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