VHDL Enhancements 
Author Message
 VHDL Enhancements

When thinking about modelling bi-directional devices like pass transistors and transmission gates for CMOS VLSI circuits, it struck me that VHDL does not have
a mechanism for identifying the driver responsible for an event. If the models
for such devices could identify that they had previously scheduled the events
which activated them then it would be possible to write simpler models for them.

What I had in mind was a signal attribute (e.g. 'DRIVER) which would be "true"
in the in the process(es) responsible for signal being active in a particular
cycle, and "false" in processes which did not schedule any transactions for that
cycle.

I hope this is a suitable place to discuss such issues - if not where?

-------------------------------------------------------------------------------
Kevin Cameron         INMOS, 1000 Aztec West, Almondsbury, Bristol BS12 4SQ, UK



Fri, 29 Oct 1993 23:47:42 GMT  
 VHDL Enhancements

Quote:
Cameron) writes:
>When thinking about modelling bi-directional devices like pass transistors
>and transmission gates for CMOS VLSI circuits, it struck me that VHDL does
>not have a mechanism for identifying the driver responsible for an event.
>If the models for such devices could identify that they had previously
>scheduled the events which activated them then it would be possible to
>write simpler models for them.

>What I had in mind was a signal attribute (e.g. 'DRIVER) which would be "true"
>in the process(es) responsible for signal being active in a particular
>cycle, and "false" in processes which did not schedule any transactions for
>that cycle.

Naive question: What would the use be of such a construct? It could be
useful for debugging, but what would be the intuition behind the construct
in terms of hardware?
How would you simplify the model for transistor level? As I understand the
previous paragraphs, it would mean writing a VHDL program, and then, using
the 'DRIVER attribute determine which drivers have been used in the
computation of the behaviour of the circuit. Those drivers not fires can be
deleted. Is that correct? If this understanding is correct, mustn't you do
an exhaustive simulation to determine redundant drivers?

I have the impression that VHDL's bi-directional features are used mainly
as very high level buses or as very low level bidirectional wires (as
above). Am I wrong or is there anything in between?

Disclaimer: I am not a hardware designer, but am interested in VHDL from a
(hardware Description) Language point of view. I would be grateful if
someone could post a transistor level description of a NAND gate (say)
using more than one signal strength, overpowering and stored charge on the
wires, for example?
Is VHDL used to model circuits as such a low level, or are specialised
simulators like MOSSIM (not detailed enough?) or SPICE (too detailed?)
used?

Quote:
>I hope this is a suitable place to discuss such issues - if not where?

If this isn't the right place, please let me know too...

Quote:
>Kevin Cameron   INMOS, 1000 Aztec West, Almondsbury, Bristol BS12 4SQ, UK

Kees

--
Kees Goossens                       Keep in Touch with the Dutch:

University of Edinburgh, Scotland   UUCP:  ..!mcsun!ukc!lfcs!kgg
Wiskunde is bouwen in de geest. --- Luitzen Egbertus Jan Brouwer.



Sat, 30 Oct 1993 22:33:35 GMT  
 
 [ 2 post ] 

 Relevant Pages 

1. VHDL Enhancements ('DRIVER)

2. OO enhancements to VHDL

3. VHDL Modeling Enhancement Initiative

4. Xemacs VHDL mode (vhdl.zip file, 83 Kbytes) - vhdl.zip (1/1)

5. Enhancement idea: Filter Class Methods

6. URLPresenter enhancement

7. Proposal for J enhancement

8. Enhancement request

9. Another Debugger Enhancement Request

10. Enhancement Request of Debugger

11. Enhancement request

 

 
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