comparison with xxxx 
Author Message
 comparison with xxxx

Quote:


>> I am trying to compare a data stream to check if its
>> xxxx so I say

>>        if (data==16'hxxxx)

>> compiler warns me saying this is redundant comparison
>> which leaves me stranded as to how I look for xxxx
>> condition which leaves me grounded

>Comparison to any x or z cases requires use of the
>case equality operator, ===.

>Note that this construct is not supported for synthesis.

Tell me exactly how you'd made hardware to test for the 'xxxx'
condition, and I make sure this info makes it to those who
make and sell synthesis tools.  :^)

                           - John Cooley
                             Part Time EDA Consumer Advocate
                             Full Time ASIC, FPGA & EDA Design Consultant

============================================================================
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    (  >  )
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     _] [_         Verilog, VHDL and numerous Design Methodologies.

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Wed, 23 Jan 2002 03:00:00 GMT  
 comparison with xxxx
You want to use the case equality operator,

if(data === 16'hxxxx)

Josh

Quote:


> >> I am trying to compare a data stream to check if its
> >> xxxx so I say

> >>        if (data==16'hxxxx)

> >> compiler warns me saying this is redundant comparison
> >> which leaves me stranded as to how I look for xxxx
> >> condition which leaves me grounded

> >Comparison to any x or z cases requires use of the
> >case equality operator, ===.

> >Note that this construct is not supported for synthesis.



Wed, 23 Jan 2002 03:00:00 GMT  
 comparison with xxxx

Quote:

> >> I am trying to compare a data stream to check if its
> >> xxxx so I say

> >>        if (data==16'hxxxx)

> >> compiler warns me saying this is redundant comparison
> >> which leaves me stranded as to how I look for xxxx
> >> condition which leaves me grounded

> Tell me exactly how you'd made hardware to test for the 'xxxx'
> condition, and I make sure this info makes it to those who
> make and sell synthesis tools.  :^)

>                            - John Cooley

    At first I was a  bit surprised to see this name in a _VHDL_ group ;-) But
this seems to be the magic of crossposting.

Secondly , in Verilog the construct should be '===' (3 of them). In VHDL , you
could do with a "=".

At last , it is true that this construct doesn't make sense for synthesis. But
it could make a lot of sense in a good testbench development. And testbench code
is at least as important as code to be synthesized.

Kind regards,

Jos De Laender

Quote:

>                              Part Time EDA Consumer Advocate
>                              Full Time ASIC, FPGA & EDA Design Consultant

> ============================================================================
>  Trapped trying to figure out a Synopsys bug?  Want to hear how 6000+ other
>  users dealt with it ?  Then join the E-Mail Synopsys Users Group (ESNUG)!


>      /o o\  /  it's a FEATURE!"                 (508) 429-4357
>     (  >  )
>      \ - /     - John Cooley, EDA & ASIC Design Consultant in Synopsys,
>      _] [_         Verilog, VHDL and numerous Design Methodologies.

>      Holliston Poor Farm, P.O. Box 6222, Holliston, MA  01746-6222
>    Legal Disclaimer: "As always, anything said here is only opinion."
>  The complete, searchable ESNUG Archive Site is at http://www.DeepChip.com



Fri, 25 Jan 2002 03:00:00 GMT  
 
 [ 3 post ] 

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