Synthesis Problems 
Author Message
 Synthesis Problems

Hello there,
when I try to synthesize my design, I get an error and a warning.
Can anyone help with these?
I synthesize it for Xiling Virtex (V100PQ240)

FOR something: something USE ENTITY WORK.something(rtl);

I get a warning : Configuration specifications are not supported for
synthesis

to_stdlogicvector(a) => b

I get an error : Type conversion associations is not supported in synthesis

Thanks in advance for your help



Tue, 28 Jan 2003 03:00:00 GMT  
 Synthesis Problems

Quote:

> Hello there,
> when I try to synthesize my design, I get an error and a warning.
> Can anyone help with these?
> I synthesize it for Xiling Virtex (V100PQ240)

> FOR something: something USE ENTITY WORK.something(rtl);

> I get a warning : Configuration specifications are not supported for
> synthesis

This means that your synthesizer will ignore the configuration
specification and use its own default configuration scheme (probably
names based, that is, the component and the bound entity have the
same name, there is only one architecture per entity, etc.)

Quote:

> to_stdlogicvector(a) => b

> I get an error : Type conversion associations is not supported in synthesis

Could you give some more info on the above statement. What are you
trying to do?

Regards,
--
Renaud Pacalet, ENST / COMELEC, 46 rue Barrault 75634 Paris Cedex 13



Tue, 28 Jan 2003 03:00:00 GMT  
 
 [ 2 post ] 

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