Open Collector o/p in ViewLogic VHDL 
Author Message
 Open Collector o/p in ViewLogic VHDL

Hi there!

        I would like to know how to implement open-collector outputs in VHDL.
More specifically, I am implementing all standard components ( 74LS series)
using ViewLogic VHDL. When I tried to implement the 7447 BCD_2_7Seg Decoder,
I faced this open collector output pin problem. Can anyone help me in this

Thank You in Advance!


Subramanian S. Meiyappan
Graduate Student in EE
P.O. Box 5926,
Tennessee Technological University
Cookeville, TN 38505

Thu, 19 Mar 1998 03:00:00 GMT  
 Open Collector o/p in ViewLogic VHDL
In VHDL, an open collector is modeled as a driver with 2 values ('0', and
'Z'). Thus, using Std_Logic_1164 package,  a port of type Std_Logic would
have the following values:
     '0'    for  asserted,
     'Z'   for unasserted.
The driver cannot have the value '1', since it's open collector.  

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Thu, 19 Mar 1998 03:00:00 GMT  
 [ 2 post ] 

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